New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design

IEEE Transactions on Advanced Packaging

Volumn 23, Issue 2, 2000, Pages 303-312

  Eo, Yungseon ^a   Eisenstadt, William R ^b   Jeong, Ju Young ^c   Kwon, Oh Kyong ^d  

^a Hanyang University   (South Korea)

^b University of Florida   (United States)

^c Suwon University   (South Korea)

^d Hanyang University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE; SWITCHING;

CURRENT SLEW RATE; LEAD INDUCTANCE; LOAD CAPACITANCE; SIMULTANEOUS SWITCHING NOISE ANALYSIS;

ELECTRONICS PACKAGING;

EID: 0033700783     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.846649     Document Type: Article

References (20)

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