Electrical Packaging Requirements for Low-Voltage ICs—3.3 V High-Performance CMOS Devices as a Case Study

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 17, Issue 4, 1994, Pages 493-504

  Mehra, Aran ^a   Mahalingam, Mali ^b   Doi, Yutaka ^b   Astrain, Hector ^b  

^a MOTOROLA INC   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; ELECTRIC DELAY LINES; ELECTRIC LINES; ELECTRIC LOADS; ELECTRONICS PACKAGING; ENERGY DISSIPATION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROBABILITY; SIGNAL NOISE MEASUREMENT; SWITCHING;

BALL GRID ARRAY; COMPUTATIONAL THROUGHPUT; ELECTRICAL PACKAGING; OFF CHIP DRIVER DELAY; PACKAGE INTERCONNECT; PIN GRID ARRAY; PORTABLE SYSTEMS; QUAD FLAT; RECEIVER DYNAMIC NOISE IMMUNITY; SIMULTANEOUS SWITCHING NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 0028546263     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.338714     Document Type: Article

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