Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time considerations

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 19, Issue 3, 1996, Pages 481-486

  Yang, Yaochao ^a,b   Brews, John R ^a,c  

^a IEEE

^b HEWLETT PACKARD ENTERPRISE   (United States)

^c University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; NUMERICAL METHODS; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS; TRANSISTORS;

OFF CHIP DRIVER; SIMULTANEOUS SWITCHING NOISE; SWITCHING TIME;

CMOS INTEGRATED CIRCUITS;

EID: 0030214224     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.533886     Document Type: Article

References (6)

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3. M. Annaratone, Digital CMOS Circuit Design. Boston, MA: Kluwer Academic, 1986, ch. 7, p. 261.
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6. T. Sudo, "Present and future directions for multichip module technologies," IEEE J. Solid-State Circuits, vol. SC-30, no. 4, pp. 436-442, Apr. 1995.