Accurate simultaneous switching noise estimation including velocity-saturation effects

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 19, Issue 2, 1996, Pages 344-349

  Vemuru, Srinivasa R ^a,b  

^a IEEE

^b City University of New York   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC LINES; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; PARAMETER ESTIMATION; SPURIOUS SIGNAL NOISE; SWITCHING SYSTEMS;

CHIP PACKAGE PIN INTERFACE; OUTPUT DRIVER; PARASITIC INDUCTANCE; SPICE SIMULATION; SWITCHING NOISE ESTIMATION; SWITCHING TRANSIENT CURRENTS; VELOCITY SATURATION EFFECTS; VOLTAGE SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 0030142921     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.496038     Document Type: Article

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