Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 12, 1993, Pages 1383-1388

  Senthinathan, R ^a   Prince, J L ^b  

^a MOTOROLA INC   (United States)

^b UNIVERSITY OF ARIZONA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; PULSE CIRCUITS; SOLID STATE DEVICES;

CLOCKED PULSES; CSR OUTPUT DRIVERS; SWITCHING NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 0027816393     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.262016     Document Type: Article

References (11)

1. R. Senthinathan and R. Yach, “High-speed 1 μm output driver design methodology,” Intel Corporation: Technical Report, Sept. 1988.
2. R. Senthinathan and J. L. Prince, “Simultaneous switching ground noise calculation for packaged CMOS devices,” IEEE J. Solid-State Circuits, vol. 26, p. 1724, Nov. 1991.
3. I. Tomioka et al., “Current control buffer for multiswitching CMOS SOG,” in Proc. 1990 IEEE Custom Integrated Circuit Conf., May 1990, p. 11.7.1.
4. K. Leung, “Controlled slew rate output buffer,” in Proc. 1988 IEEE Custom Integrated Circuit Conf., May 1988, p. 5.3.3.
5. N. Raver, “Open-loop gain limitations for push-pull off-chip drivers,” IEEE J. Solid-State Circuits, vol. SC-22, no. 2, p. 145, Apr. 1987.
6. M. Hashimoto and O. Kwon, “Low di/dt noise and reflection free CMOS signal driver,” in Proc. 1989 IEEE Custom Integrated Circuit Conf., May 1989, p. 14.4.1.
7. R. Senthinathan, J. L. Prince, and S. Nimmagadda, “Noise immunity characteristics of CMOS receivers and effects of skewing/damping CMOS output driver switching waveform on the simultaneous switching noise,” Microelectronics J., vol. 23, no. 1, p. 29, March 1992.
8. D. A. Hodges and H. G. Jackson, Analysis and Design of Digital Integrated Circuits, New York: McGraw-Hill, 1983.
9. M. Shoji, CMOS Digital Circuit Technology. Englewood Cliffs, NJ: Prentice-Hall, 1988.
10. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 1984.
11. J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Trans. Computer-Aided Design, vol. CAD-2, p. 202, July 1983.