-
4
-
-
84886448151
-
Full copper wiring in a sub-0.25 micron CMOS ULSI technology
-
D. Edelstein et al., "Full copper wiring in a sub-0.25 micron CMOS ULSI technology," in Int. Electron Devices Meeting, 1997, pp. 773-776.
-
(1997)
Int. Electron Devices Meeting
, pp. 773-776
-
-
Edelstein, D.1
-
5
-
-
0031695978
-
Copper interconnects and reliability
-
C. K. Hu and J. M. E. Harper, "Copper interconnects and reliability," Materials, Chemistry, Phys., vol. 52, pp. 5-16, 1998.
-
(1998)
Materials, Chemistry, Phys.
, vol.52
, pp. 5-16
-
-
Hu, C.K.1
Harper, J.M.E.2
-
6
-
-
58149212969
-
-
S. P. Murarka and R. J. Gutmann, Eds.
-
S. P. Murarka and R. J. Gutmann, Eds., Copper Metallization for Future VLSI, Materials Chemistry, Phys. (Special Issue), vol. 41, pp. 159-228, 1995.
-
(1995)
Copper Metallization for Future VLSI, Materials Chemistry, Phys. (Special Issue)
, vol.41
, pp. 159-228
-
-
-
7
-
-
33747357434
-
-
1995.
-
T. A. Alford, J. Li, J. W. Mayer, and S.-Q. Wang, Eds., Copper-Based Metallization and Interconnects, Thin Solid Films (Special Issue), vol. 262, pp. 1-242, 1995.
-
J. Li, J. W. Mayer, and S.-Q. Wang, Eds., Copper-Based Metallization and Interconnects, Thin Solid Films (Special Issue), Vol. 262, Pp. 1-242
-
-
Alford, T.A.1
-
8
-
-
0032166781
-
-
1998.
-
P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, "Damascene copper electroplating for chip interconnections," IBM J., vol. 42, pp. 557-574, 1998.
-
C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, "Damascene Copper Electroplating for Chip Interconnections," IBM J., Vol. 42, Pp. 557-574
-
-
Andricacos, P.C.1
-
10
-
-
0029512530
-
-
1995.
-
R. J. Gutmann et al, "Integration of copper multilevel interconnects with oxide and polymer interlevel dielectrics," Thin Solid Films, vol. 270, pp. 472-79, 1995.
-
Et Al, "Integration of Copper Multilevel Interconnects with Oxide and Polymer Interlevel Dielectrics," Thin Solid Films, Vol. 270, Pp. 472-79
-
-
Gutmann, R.J.1
-
11
-
-
0031248720
-
-
1997.
-
D. T. Price, R. J. Gutmann, and S. P. Murarka, "Damascene copper interconnect with polymer ILD's," Thin Solid Films, vol. 308-309, pp. 523-528, 1997.
-
R. J. Gutmann, and S. P. Murarka, "Damascene Copper Interconnect with Polymer ILD's," Thin Solid Films, Vol. 308-309, Pp. 523-528
-
-
Price, D.T.1
-
13
-
-
0031256176
-
-
1997.
-
W. W. Lee and P. S. Ho, "Low-dielectric constant materials for ULSI interlayer dielectric applications," Mater. Res. Bull., vol. 22, pp. 19-23, 1997.
-
And P. S. Ho, "Low-dielectric Constant Materials for ULSI Interlayer Dielectric Applications," Mater. Res. Bull., Vol. 22, Pp. 19-23
-
-
Lee, W.W.1
-
14
-
-
0029205036
-
-
pp. 177-195.
-
R. J. Gutmann et al., "Low dielectric constant polymers for on-chip interlevel dielectrics with copper metallization," in Proc. Materials Res. Soc., vol. 381, 1995, pp. 177-195.
-
Et Al., "Low Dielectric Constant Polymers for On-chip Interlevel Dielectrics with Copper Metallization," in Proc. Materials Res. Soc., Vol. 381, 1995
-
-
Gutmann, R.J.1
-
16
-
-
33746991507
-
-
Nov. 1992.
-
B. Myerson, "UHV/CVD growth of Si and SiGe alloys: Chemistry, physics and device applications," Proc. IEEE, vol. 80, pp. 1592-1608, Nov. 1992.
-
"UHV/CVD Growth of Si and SiGe Alloys: Chemistry, Physics and Device Applications," Proc. IEEE, Vol. 80, Pp. 1592-1608
-
-
Myerson, B.1
-
18
-
-
33747341239
-
-
Mar. 1995.
-
D. L. Harame et al., "Si/SiGe epitaxial-base transistors," IEEE Trans. Electron Devices, vol. 40, pp. 455-182, Mar. 1995.
-
Et Al., "Si/SiGe Epitaxial-base Transistors," IEEE Trans. Electron Devices, Vol. 40, Pp. 455-182
-
-
Harame, D.L.1
-
21
-
-
33747363919
-
-
Oct. 1998.
-
P. Jain, J. Turley, V. Agarwal, F. Bond, and P. Varhol, "Key technology and design issues," Comput. Design, pp. 40-74, Oct. 1998.
-
J. Turley, V. Agarwal, F. Bond, and P. Varhol, "Key Technology and Design Issues," Comput. Design, Pp. 40-74
-
-
Jain, P.1
-
23
-
-
33747370306
-
-
May 1998.
-
R. Subbu, A. C. Sanderson, C. Hocaoglu, and R. J. Graves, "Distributed Virtual Design Environment using intelligent agent architecture," in Proc. Industrial Eng. Res. Conf., May 1998.
-
A. C. Sanderson, C. Hocaoglu, and R. J. Graves, "Distributed Virtual Design Environment Using Intelligent Agent Architecture," in Proc. Industrial Eng. Res. Conf.
-
-
Subbu, R.1
-
25
-
-
0025474604
-
-
Aug. 1990.
-
N. M. Nguyen and R. G. Meyer, "Si IC-compatible inductors and LC passive filters," IEEE J. Solid-State Circuits, vol. 25, pp. 1028-1031, Aug. 1990.
-
And R. G. Meyer, "Si IC-compatible Inductors and LC Passive Filters," IEEE J. Solid-State Circuits, Vol. 25, Pp. 1028-1031
-
-
Nguyen, N.M.1
-
26
-
-
0029373824
-
-
Dec. 1995.
-
A. C. Reyes et al., "Coplanar waveguides and microwave inductors on silicon substrates," IEEE Trans. Microwave Theory Tech., vol. 43, pp. 2016-2021, Dec. 1995.
-
Et Al., "Coplanar Waveguides and Microwave Inductors on Silicon Substrates," IEEE Trans. Microwave Theory Tech., Vol. 43, Pp. 2016-2021
-
-
Reyes, A.C.1
-
27
-
-
0030243085
-
-
Sept. 1996.
-
J. N. Burghartz, K. A. Jenkins, and M. Soyuer, "Multilevel-spiral inductors using VLSI interconnect technology," IEEE Electron Device Lett., vol. 17, pp. 428-30, Sept. 1996.
-
K. A. Jenkins, and M. Soyuer, "Multilevel-spiral Inductors Using VLSI Interconnect Technology," IEEE Electron Device Lett., Vol. 17, Pp. 428-30
-
-
Burghartz, J.N.1
-
28
-
-
0030241682
-
-
June 1996.
-
R. A. Johnson et al., "Comparison of microwave inductors fabricated on silicon-on-sapphire and bulk silicon," IEEE Microwave Guided Wave Lett., vol. 6, pp. 323-325, June 1996.
-
Et Al., "Comparison of Microwave Inductors Fabricated on Silicon-on-sapphire and Bulk Silicon," IEEE Microwave Guided Wave Lett., Vol. 6, Pp. 323-325
-
-
Johnson, R.A.1
-
29
-
-
0031249261
-
-
Oct. 1997.
-
J. N. Burghartz, D. C. Edelstein, K. A. Jenkins, and Y. H. Kwark, "Spiral inductors and transmission lines in silicon technology using copper-damascene interconnects and low-loss substrates," IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1961-1968, Oct. 1997.
-
D. C. Edelstein, K. A. Jenkins, and Y. H. Kwark, "Spiral Inductors and Transmission Lines in Silicon Technology Using Copper-damascene Interconnects and Low-loss Substrates," IEEE Trans. Microwave Theory Tech., Vol. 45, Pp. 1961-1968
-
-
Burghartz, J.N.1
-
30
-
-
0032070684
-
-
May 1998.
-
R. Gotzfried et al, "RFIC's for mobile communication systems using SiGe bipolar technology," IEEE Trans. Microwave Theory Tech., vol. 46, pp. 661-668, May 1998.
-
Et Al, "RFIC's for Mobile Communication Systems Using SiGe Bipolar Technology," IEEE Trans. Microwave Theory Tech., Vol. 46, Pp. 661-668
-
-
Gotzfried, R.1
-
32
-
-
0031246188
-
-
Oct. 1997.
-
A. Deutsch étal, "When are transmission-line effects important for onchip interconnects," IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997.
-
Étal, "When Are Transmission-line Effects Important for Onchip Interconnects," IEEE Trans. Microwave Theory Tech., Vol. 45, Pp. 1836-1846
-
-
Deutsch, A.1
-
33
-
-
0031249223
-
-
Oct. 1997.
-
J.-G. Yook et at., "Application of system-level EM modeling to highspeed digital 1C packages and PCB's," IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1847-1856, Oct. 1997.
-
Et At., "Application of System-level EM Modeling to Highspeed Digital 1C Packages and PCB's," IEEE Trans. Microwave Theory Tech., Vol. 45, Pp. 1847-1856
-
-
Yook, J.-G.1
-
34
-
-
0028259903
-
-
June 1994.
-
J. S. Roychowdury, A. R. Newton, and D. O. Pederson, "Algorithms for the transient simulation of lossy interconnects," IEEE Trans. ComputerAided Design, vol. 13, pp. 96-104, June 1994.
-
A. R. Newton, and D. O. Pederson, "Algorithms for the Transient Simulation of Lossy Interconnects," IEEE Trans. ComputerAided Design, Vol. 13, Pp. 96-104
-
-
Roychowdury, J.S.1
|