Damascene copper electroplating for chip interconnections

IBM Journal of Research and Development

Volumn 42, Issue 5, 1998, Pages 567-573

  Andricacos, P C ^a,b,c   Uzoh, C ^a,d,e,f,g   Dukovic, J O ^a,b,e,h,i,j   Horkans, J ^a,h,k   Deligianni, H ^l  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM Thomas J Watson Research Center ^*  (United States)

^c LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^d IBM MICROELECTRONICS   (United States)

^e IBM   (United States)

^f UNIVERSITY OF WISCONSIN MADISON   (United States)

^g RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^h CASE WESTERN RESERVE UNIVERSITY   (United States)

ⁱ UNIVERSITY OF CALIFORNIA   (United States)

^j ELECTROCHEMICAL SOCIETY

^k ST OLAF COLLEGE   (United States)

^l Columbia University ^*

more..

Author keywords

[No Author keywords available]

Indexed keywords

COPPER PLATING; ELECTRIC WIRING; MATHEMATICAL MODELS;

CHIP INTERCONNECTIONS; DAMASCENE COPPER ELECTROPLATING; SUPERFILLING;

ELECTROPLATING;

EID: 0032166781     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.425.0567     Document Type: Article

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