An asymmetrically doped buried-layer (adb) structure for low-voltage mixed analog-digital cmos lsi's

IEEE Transactions on Electron Devices

Volumn 46, Issue 8, 1999, Pages 1699-1704

  Miyamoto, Masafumi ^a   Toyota, Kenji ^a   Seki, Koichi ^b  

^a IEEE

^b HITACHI LTD   (Japan)

Author keywords

Asymmetrically doped buried layer (adb); Drain junction capacitance; Drain output resistance; Low voltage power supply; Saturation current; Transconductance

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS; LSI CIRCUITS; MIXER CIRCUITS; MOSFET DEVICES; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

ASYMMETRICALLY DOPED BURIED LAYER; DRAIN JUNCTION CAPACITANCE; DRAIN OUTPUT RESISTANCE; DRAIN SIDE CHANNEL REGION; LOW VOLTAGE POWER SUPPLY; SATURATION CURRENT;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0033169526     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.777159     Document Type: Article

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