0.3-µm Mixed Analog/Digital CMOS Technology for Low-Voltage Operation

IEEE Transactions on Electron Devices

Volumn 41, Issue 10, 1994, Pages 1837-1842

  Ishii, Tatsuya ^a   Miyamoto, Masafumi ^a   Nagai, Ryo ^a   Nishida, Takashi ^a   Seki, Koichi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC INSULATORS; GATES (TRANSISTOR); ION IMPLANTATION; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SURFACES;

ANALOG/DIGITAL CMOS TECHNOLOGY; DOUBLE POLYSILICON CAPACITOR; HIGH CURRENT DRIVABILITY; INSULATOR THICKNESS; LATERALLY DOPED BURIED LAYER; LOW VOLTAGE OPERATION; MOSFET STRUCTURE;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0028517042     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.324596     Document Type: Article

References (9)

1. M. Miyamoto. T. Ishii, R. Nagai, T. Nishida, and K. Seki, “0.3-µtm mixed analog/digital CMOS technology for low-voltage operation,” in Proc. CICC. 1993, p. 24.4.
2. M. Aoki. T. Ishii, Y. Yoshimura, Y. Kiyota, S. Iijima, T. Yokoyama, T. Kure. K. Ohyu, T. Nishida, S. Okazaki, K. Seki, and K. Shimohigashi, “0. 1-µm CMOS devices using low-impurity channel transistors (LICT),” in IEDM Tech. Dig. 1990, p. 939.
3. R. Izawa, D. Hisamoto, and E. Takeda, “Substrate engineering for Vth-scaling at low supply voltage (1.5-3 V) in ULSIs,” in Proc. SSDM, 1989, p. 121.
4. Y. Okumura, M. Shirahata, T. Okudaira, A. Hachisuka, H. Arima, T. Matsukawa, and N. Tsubouchi, “A novel source-to-drain NonUniformly Doped Channel (NUDC) MOSFET for high current and threshold voltage controllability,” in IEDM Tech. Dig., 1990, p. 391.
5. S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1982.
6. J. L. McCreary, “Matching properties, and voltage and temperature dependence of MOS capacitor,” IEEE J. Solid-State Circuit, vol. SC-16, p. 608, 1981.
7. D. K. Sadana, A. Acvic, G. Shahidi, H. Hanafi, A. C. Warren, D. Grutzmacher, F. Cardone, J. Sun, and B. Davari, “Enhanced short-channel effect in NMOSFETs due to boron redistribution induced by arsenic source and drain implant,” in IEDM Tech. Dig., 1992, p. 849.
8. H. I. Hanafi, W. P. Noble, R. S. Bass, K. Varahramyan, Y. Lii, and A. J. Darry. “A model for anomalous short-channel behavior in submicron MOSFET’s,” IEEE Electron Device Lett., vol. 12, p. 575, 1993.
9. T. Matsuura, K. Yano, M. Hiraki, Y. Sasaki, M. Miyamoto, T. Ishii, R. Nagai, T. Nishida, K. Seki, E. Imaizumi, T. Anbo, N. Sumi, and K. Rikino, “1.2 V mixed analog/digital circuits using 0.3 µm CMOS LSI technology,” in ISSCC Dig. Tech. Papers, 1994, p. 250.