Simulation and Fabrication of Submicron Channel Length DMOS Transistors for Analog Applications

IEEE Transactions on Electron Devices

Volumn 40, Issue 12, 1993, Pages 2222-2230

  Hong, Merit Y ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CASCADE CONNECTIONS; DIFFUSION IN SOLIDS; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; LINEAR INTEGRATED CIRCUITS; OPERATIONAL AMPLIFIERS; PROCESS CONTROL; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SUBSTRATES; TRANSISTORS;

DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR (DMOS) TRANSISTORS; IMPLANTATION ANGLE; INTRINSIC GAIN; OUTPUT RESISTANCE; SUBMICRON CHANNEL LENGTH; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

MOS DEVICES;

EID: 0027803916     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.249469     Document Type: Article

References (11)

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