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Volumn 42, Issue 9, 1995, Pages 1614-1622

Theoretical Analysis and Modeling of Submicron Channel Length DMOS Transistors

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC FIELDS; FREQUENCY RESPONSE; GATES (TRANSISTOR); MOS DEVICES; NUMERICAL ANALYSIS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0029379418     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.405275     Document Type: Article
Times cited : (8)

References (12)
  • 1
    • 0027803916 scopus 로고
    • Simulation and fabrication of submicron channel length DMOS transistors for analog applications
    • M. Y. Hong, “Simulation and fabrication of submicron channel length DMOS transistors for analog applications,” IEEE Trans. Electron Devices vol. 40, pp. 2122–2130, 1993.
    • (1993) IEEE Trans. Electron Devices , vol.40 , pp. 2122-2130
    • Hong, M.Y.1
  • 2
    • 20444489132 scopus 로고
    • A high-performance scalable submicron MOSFET for mixed analog digital applications
    • L. T. Su, J. A. Yasaitis, D. A. Antoniadis, “A high-performance scalable submicron MOSFET for mixed analog digital applications,” IEDM Tech. Dig., pp. 367–370, 1991.
    • (1991) IEDM Tech. Dig. , pp. 367-370
    • Su, L.T.1    Yasaitis, J.A.2    Antoniadis, D.A.3
  • 3
    • 0024870094 scopus 로고
    • Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance
    • T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, C. F. Codella, “Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance,” IEDM Tech. Dig., pp. 617–620, 1989.
    • (1989) IEDM Tech. Dig. , pp. 617-620
    • Buti, T.N.1    Ogura, S.2    Rovedo, N.3    Tobimatsu, K.4    Codella, C.F.5
  • 5
    • 84938445633 scopus 로고
    • Device design of E/D gate MOSFET
    • Tokyo, Japan, also supplement to J. Japan Soc. Appl. Phys., vol. 42, 1973, pp. 167–172
    • H. Masuda, T. Masuhara, M. Nagata, N. Hashimoto, “Device design of E/D gate MOSFET,” in Proc. 4th Conf. on Solid State Devices, Tokyo, Japan, 1972; also supplement to J. Japan Soc. Appl. Phys., vol. 42, 1973, pp. 167–172.
    • (1972) Proc. 4th Conf. on Solid State Devices
    • Masuda, H.1    Masuhara, T.2    Nagata, M.3    Hashimoto, N.4
  • 9
    • 84938444347 scopus 로고
    • Double diffused (DMOS) FET's for analog applications
    • Ph.D. dissertation, Massachusetts Institute of Technology, Cambridge
    • M. Y. Hung, “Double diffused (DMOS) FET's for analog applications,” Ph.D. dissertation, Massachusetts Institute of Technology, Cambridge, 1990.
    • (1990)
    • Hung, M.Y.1
  • 10
    • 11744363063 scopus 로고
    • MOSFET modeling for circuit simulation
    • N. G. Einspruch and G. Gildenblat, Eds. San Diego, CA: Academic Press
    • N. D. Arora, L. M. Richardson, “MOSFET modeling for circuit simulation,” in Advanced MOS Device Physics, N. G. Einspruch and G. Gildenblat, Eds. San Diego, CA: Academic Press, 1989, vol. 18, pp. 237–276.
    • (1989) Advanced MOS Device Physics , vol.18 , pp. 237-276
    • Arora, N.D.1    Richardson, L.M.2
  • 11
    • 0018195506 scopus 로고
    • Increase of gate capacitance in DMOST
    • E. F. Stikvoort, “Increase of gate capacitance in DMOST,” IEEE Trans. Electron Devices, vol. ED-25, pp. 1388–1394, 1978.
    • (1978) IEEE Trans. Electron Devices , vol.ED-25 , pp. 1388-1394
    • Stikvoort, E.F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.