Rapid thermal anneal of gate oxides for low thermal budget TFT's

IEEE Transactions on Electron Devices

Volumn 46, Issue 1, 1999, Pages 63-69

  Bhat, Navakanta ^a   Wang, Albert W ^b   Saraswat, Krishna C ^c  

^a Stanford University   (United States)

^b MOTOROLA INC   (United States)

^c Packard Company   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARGON; CHEMICAL VAPOR DEPOSITION; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC CHARGE; FOURIER TRANSFORM INFRARED SPECTROSCOPY; GATES (TRANSISTOR); NITROGEN OXIDES; OXYGEN; RAPID THERMAL ANNEALING; SEMICONDUCTOR DEVICE MANUFACTURE; THERMAL EFFECTS; THERMODYNAMIC STABILITY;

CHARGE PUMPING TECHNIQUES; LOW PRESSURE CHEMICAL VAPOR DEPOSITION (LPCVD);

THIN FILM TRANSISTORS;

EID: 0032740569     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.737442     Document Type: Article

References (17)

1. M. Takabatake, J. Ohwada, Y. A. Ono, A. Mimura, and N. Konishi, CMOS circuits for peripheral circuit integrated poly-Si TFT LCD fabricated at low temperature below 600 °C, IEEE Trans. Electron Devices, vol. 38, p. 1303, June 1991.
2. S. Ikeda, S. Hashiba, I. Kuramoto, H. Katoh, S. Ariga, T. Yamanaka, T. Hashimoto, N. Hashimoto, and S. Meguro, A polysilicon transistor technology for large capacity SRAM's, in IEDM Tech. Dig., 1990, p. 469.
3. W. H. Dumbaugh and P. L. Bocko, Substrate glasses for flat panel displays, in Proc. Soc. Inform. Display, vol. 31, no. 4, p. 269, 1990.
4. S. M. Sze, VLSI Technology, 2nd ed. New York: McGraw-Hill, 1988.
5. M. Bonnel, N. Duhamel, M. Guendouz, L. Haji, B. Loisel, and P. Ruault, Poly-Si thin film transistors fabricated with rapid thermal annealed silicon films, Jpn. J. Appl. Phys., vol. 30, no. 11B, p. L1924, 1991
6. N. Bhat, P. P. Apte, and K. C. Saraswat, Charge trap generation in LPCVD oxides under high field stressing, IEEE. Trans. Electron Devices, vol. 43, p. 554, Apr. 1996.
7. 2/Si interface in structures prepared by thermal oxidation of Si and subjected to rapid thermal annealing, J. Vac. Sci. Technol. B, vol. 7, no. 4, p. 775, 1989.
8. W. A. Pliskin and H. S. Lehman, Structural evaluation of silicon oxide films, J. Electrochem. Soc., vol. 112, no. 10, p. 1013, 1965.
9. M. Cao, T. Zhao, K. C. Saraswat, and J. D. Plummer, Study on hydrogénation of polysilicon thin film transistors by ion implantation, IEEE. Trans. Electron Devices, vol. 42, p. 1134, June 1995.
10. M. Koyanagi, I.-W. Wu, A. G. Lewis, M. Fuse, and R. Bruce, Evaluation of polycrystalline silicon thin film transistors with the charge pumping technique, in IEDM Tech. Dig., 1990, p. 863.
11. D.-B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat, Twodimensional thermal oxidation of silicon. II. Modeling stress effects in wet oxides, IEEE. Trans. Electron Devices, vol. 35, p. 25, 1988.
12. Z.-J. Ma, Z. H. Liu, J. T. Crick, H. J. Huang, Y. C. Cheng, C. Hu, and P. K. Ko, Optimization of gate oxide N2O anneal for CMOSFET's at room and cryogenic temperatures, IEEE. Trans. Electron Devices, vol. 41, p. 1364, Aug. 1994.
13. P. P. Apte and K. C. Saraswat, Correlation of trap generation to charge to breakdown (Qbd)'- A physical damage model of dielectric breakdown, IEEE. Trans. Electron Devices, vol. 41, p. 1595, Sept. 1994.
14. G. Lucovsky, M. J. Manitini, J. K. Srivastava, and E. A. Irene, Lowtemperature growth of silicon dioxide films: A study of chemical bonding by ellipsometry and infrared spectroscopy, J. Vac. Sci. Technol. B, vol. 5, no. 2, p. 530, 1987.
15. N. Bhat, M. Cao, and K. C. Saraswat, Bias temperature instability in hydrogenated thin film transistors, IEEE Trans. Electron Devices, vol. 44, p. 1102, July 1997.
16. J. T. Yount and P. M. Lenahan, personal communications.
17. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, A reliable approach to charge pumping measurements in MOS transistors, IEEE Trans. Electron Devices, Vol. ED31, p. 42, Jan. 1984.