Charge trap generation in LPCVD oxides under high field stressing

IEEE Transactions on Electron Devices

Volumn 43, Issue 4, 1996, Pages 554-560

  Bhat, Navakanta ^a   Apte, Pushkar P ^a   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; DEGRADATION; ELECTRIC BREAKDOWN; ELECTRIC CHARGE; ELECTRIC CONDUCTIVITY; ELECTRIC CURRENTS; ELECTRODES; GATES (TRANSISTOR); SILICATES; STRESSES; SYNTHESIS (CHEMICAL);

CHARGE TRAP GENERATION; FLATBAND VOLTAGE; FOWLER-NORDHEIM TUNNELING CURRENT; GATE VOLTAGE; HIGH FIELD STRESSING; INTERFACE STATE DENSITY;

OXIDES;

EID: 0030130290     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.485537     Document Type: Article

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