Optimization of Gate Oxide N2O Anneal for CMOSFET’s at Room and Cryogenic Temperatures

IEEE Transactions on Electron Devices

Volumn 41, Issue 8, 1994, Pages 1364-1372

  Cheng, Y C ^d   Ko, Ping K ^c   Hu, Chenming ^c   Huang, H J ^c  

^a INTEGRATED DEVICE TECHNOLOGY INC   (United States)

^b Chrontel Inc   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CRYOGENICS; ELECTRIC VARIABLES MEASUREMENT; INTERFACES (MATERIALS); MOSFET DEVICES; NITROGEN OXIDES; OPTIMIZATION; OXIDATION; RELIABILITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICA;

CMOSFET; GATE OXIDE; NITROGEN CONCENTRATION; ROOM TEMPERATURE;

GATES (TRANSISTOR);

EID: 0028484275     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.297731     Document Type: Article

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