-
1
-
-
0027811871
-
-
1993.
-
C. Park, K. Buckmann, J. Diamond, U. Santoni, S. The, M. Holler, M. Glier, C. Scofield, and L. Nunez, "A radial basis function neural network with on-chip learning," Proc. Int. Joint Conf. on Neural Networks, pp.3035-3038, 1993.
-
K. Buckmann, J. Diamond, U. Santoni, S. The, M. Holler, M. Glier, C. Scofield, and L. Nunez, "A Radial Basis Function Neural Network with On-chip Learning," Proc. Int. Joint Conf. on Neural Networks, Pp.3035-3038
-
-
Park, C.1
-
2
-
-
0028124015
-
-
1994.
-
Y. Kondo, Y. Koshiba, Y. Arirna, M. Murasaki, T. Yamada, H. Amishiro, H. Shinohara, and H. Mori, "A 1.2GFLOPS neural network chip exhibiting fast convergence," ISSCC, pp.218-219, 1994.
-
Y. Koshiba, Y. Arirna, M. Murasaki, T. Yamada, H. Amishiro, H. Shinohara, and H. Mori, "A 1.2GFLOPS Neural Network Chip Exhibiting Fast Convergence," ISSCC, Pp.218-219
-
-
Kondo, Y.1
-
3
-
-
0031702317
-
-
1998.
-
O. Saito, K. Aihara, O. Fujita, and K. Uchimura, "A l M synapse self-learning digital neural network chip," ISSCC, pp.94-95, 1998.
-
K. Aihara, O. Fujita, and K. Uchimura, "A L M Synapse Self-learning Digital Neural Network Chip," ISSCC, Pp.94-95
-
-
Saito, O.1
-
4
-
-
85027137369
-
-
1996.
-
Y. Hirai and M. Yasunaga, "A PDM digital neural network system with 1,000 neurons fully interconnected via 1,000,000 G-bit synapses," Proc. ICONIP, pp.1251-1256, 1996.
-
And M. Yasunaga, "A PDM Digital Neural Network System with 1,000 Neurons Fully Interconnected Via 1,000,000 G-bit Synapses," Proc. ICONIP, Pp.1251-1256
-
-
Hirai, Y.1
-
5
-
-
0027641150
-
-
1993.
-
C.R. Schneider and H.C. Card, "Analog CMOS deterministic Boltzmann circuits," IEEE J. Solid-State Circuits, vol.28, pp.907-914, 1993.
-
And H.C. Card, "Analog CMOS Deterministic Boltzmann Circuits," IEEE J. Solid-State Circuits, Vol.28, Pp.907-914
-
-
Schneider, C.R.1
-
6
-
-
0028495068
-
-
1994.
-
T. Morie and Y. Amemiya, "An all-analog expandable neural network LSI with on-chip backpropagation learning," IEEE J. Solid-State Circuits, vol.29, pp.1086-1093, 1994.
-
And Y. Amemiya, "An All-analog Expandable Neural Network LSI with On-chip Backpropagation Learning," IEEE J. Solid-State Circuits, Vol.29, Pp.1086-1093
-
-
Morie, T.1
-
7
-
-
0031191573
-
-
1997.
-
T. Morie, O. Fujita, and K. Uchimura, "Self-learning analog neural network LSI with high-resolution non-volatile analog memory and a partially-serial weight-update architecture," IEICE Trans. Electron., vol.E80-C, pp.990-995, 1997.
-
O. Fujita, and K. Uchimura, "Self-learning Analog Neural Network LSI with High-resolution Non-volatile Analog Memory and A Partially-serial Weight-update Architecture," IEICE Trans. Electron., Vol.E80-C, Pp.990-995
-
-
Morie, T.1
-
8
-
-
0030086540
-
-
1996.
-
A. Iwata and M. Nagata, "A concept of analog-digital merged circuit architecture for future VLSI's," IEICE Trans. Fundamentals., vol.E79-A, no.2, pp.145-157, 1996.
-
And M. Nagata, "A Concept of Analog-digital Merged Circuit Architecture for Future VLSI's," IEICE Trans. Fundamentals., Vol.E79-A, No.2, Pp.145-157
-
-
Iwata, A.1
-
9
-
-
0031672571
-
-
1998.
-
M. Nagata, J. Funakoshi, and A. Iwata, "A PWM signal processing core circuit based on a switched current integration technique," IEEE J. Solid-State Circuits, vol.33, no.l, pp.53-60, 1998.
-
J. Funakoshi, and A. Iwata, "A PWM Signal Processing Core Circuit Based on A Switched Current Integration Technique," IEEE J. Solid-State Circuits, Vol.33, No.l, Pp.53-60
-
-
Nagata, M.1
-
10
-
-
0031186289
-
-
1997.
-
T. Morie, S. Sakabayashi, M. Nagata, and A. Iwata, "Nonlinear function generators and chaotic signal generators using a pulse-width modulation method," Electron. Lett., vol.33, no.16, pp.1351-1352, 1997.
-
S. Sakabayashi, M. Nagata, and A. Iwata, "Nonlinear Function Generators and Chaotic Signal Generators Using A Pulse-width Modulation Method," Electron. Lett., Vol.33, No.16, Pp.1351-1352
-
-
Morie, T.1
-
11
-
-
0001553201
-
-
1990.
-
K. Aihara, T. Takabe, and M. Toyoda, "Chaotic neural networks," Phys. Lett. A, vol.144, pp.333-340, 1990.
-
T. Takabe, and M. Toyoda, "Chaotic Neural Networks," Phys. Lett. A, Vol.144, Pp.333-340
-
-
Aihara, K.1
-
12
-
-
0031140541
-
-
1997.
-
E.I. El-Masry, ILK. Yang, and M.A. Yakout, "Implementations of artificial neural networks using current-mode pulse width modulation technique," IEEE Trans. Neural Networks, vol.8, no.3, pp.532-548, 1997.
-
ILK. Yang, and M.A. Yakout, "Implementations of Artificial Neural Networks Using Current-mode Pulse Width Modulation Technique," IEEE Trans. Neural Networks, Vol.8, No.3, Pp.532-548
-
-
El-Masry, E.I.1
-
13
-
-
0031674051
-
-
1998.
-
J.C. Bor and C.Y. Wu, "Realization of the CMOS pulsewidth-modulation (PWM) neural network with onchip learning," IEEE Trans. Circuits & Syst. II, vol.45, no.l, pp.96-107, 1998.
-
And C.Y. Wu, "Realization of the CMOS Pulsewidth-modulation (PWM) Neural Network with Onchip Learning," IEEE Trans. Circuits & Syst. II, Vol.45, No.l, Pp.96-107
-
-
Bor, J.C.1
-
14
-
-
85027196730
-
-
1990.
-
PAY. Hollis, J.S. Harper, and J.J. Paulos, "The effect of precision constraints in a backpropagation learning network," Neural Computation, vol.2, pp.363-373, 1990.
-
And J.J. Paulos, "The Effect of Precision Constraints in A Backpropagation Learning Network," Neural Computation, Vol.2, Pp.363-373
-
-
Harper, J.S.1
-
15
-
-
0025548891
-
-
June 1990.
-
D.D. Caviglia, M. Valle, and G.M. Bisio, "Effects of weight discretization on the back propagation learning method: Algorithm design and hardware realization," Proc. Int. Joint Conf. on Neural Networks, pp.II-631-637, June 1990.
-
M. Valle, and G.M. Bisio, "Effects of Weight Discretization on the Back Propagation Learning Method: Algorithm Design and Hardware Realization," Proc. Int. Joint Conf. on Neural Networks, Pp.II-631-637
-
-
Caviglia, D.D.1
-
16
-
-
0026398325
-
-
July 1991.
-
[IG] J.L. Holt and J. Hwang, "Finite precision error analysis of neural network electronic hardware implementations," Proc. Int. Joint Conf. on Neural Networks, pp.I-519-525, Seattle, July 1991.
-
And J. Hwang, "Finite Precision Error Analysis of Neural Network Electronic Hardware Implementations," Proc. Int. Joint Conf. on Neural Networks, Pp.I-519-525, Seattle
-
-
Holt, J.L.1
-
17
-
-
85027155548
-
-
May 1992.
-
B.W. Lee and S.W. Kim, "Required dynamic range and accuracy of electronic synapses for character recognition applications," IEEE Proc. of Int. Symp. Circuits and Systems, pp.1545-1548, San Diego, May 1992.
-
And S.W. Kim, "Required Dynamic Range and Accuracy of Electronic Synapses for Character Recognition Applications," IEEE Proc. of Int. Symp. Circuits and Systems, Pp.1545-1548, San Diego
-
-
Lee, B.W.1
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