Self-learning analog neural network lsi with highresolution non-volatile analog memory and a partially-serial weight-update architecture

IEICE Transactions on Electronics

Volumn E80-C, Issue 7, 1997, Pages 990-995

  Morie, Takashi ^a   Fujita, Osamu ^b   Uchimura, Kuniharu ^b  

^a NTT Network Service Systems Laboratories   (Japan)

^b NTT CORPORATION   (Japan)

Author keywords

Analog lsi; Footing gate device; Neural networks; Non volatile memory

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LEARNING SYSTEMS; LSI CIRCUITS; MICROPROCESSOR CHIPS; MOSFET DEVICES; NONVOLATILE STORAGE;

BOLTZMANN MACHINES; FLOATING GATE DEVICES; HOPFIELD NETWORK;

NEURAL NETWORKS;

EID: 0031191573     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (15)

1. M. Griffin, G. Tahara, K. Knorpp, R. Pinkham, and B. Riley, An 11-million transistor neural network execution engine, IEEE Int. Solid-State Circuits Conf. Dig., pp.180-181, 1991.
2. C. Park, K. Buckmann, J. Diamond, U. Santoni, S. The, M. Holler, M. Glier, C. Scofield, and L. Nunez, A radial basis function neural network with on-chip learning, Proc. Int. Joint Conf. on Neural Networks, pp.3035-3038, 1993.
3. J. Alspector, A. Jayakumar, and S. Luna, Experimental evaluation of learning in a neural microsystem, in J.E. Moody, S.J. Hanson, and R.P. Lippmann, eds, Advances in Neural Information Processing Systems 4, pp.871-878, Morgan Kaufmann, 1992.
4. T. Shima, T. Kimura, Y. Kamatani, T. Itakura, Y. Fujita, and T. lida, Neuro chips with on-chip back-propagation and/or Hebbian learning, IEEE J. Solid-State Circuits, vol.27, pp.1868-1876, 1992.
5. Y. Arima, M. Murasaki, T. Yamada, A. Maeda, and H. Shinohara, A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses, IEEE J. SolidState Circuits, vol.27, pp.1854-1861, 1992.
6. C.R. Schneider and H.C. Card, Analog CMOS deterministic Boltzmann circuits, IEEE J. Solid-State Circuits, vol.28, pp.907-914, 1993.
7. T. Morie and Y. Amemiya, An all-analog expandable neural network LSI with on-chip backpropagation learning, IEEE J. Solid-State Circuits, vol.29, pp.1086-1093, 1994.
8. M. Holler, S. Tarn, H. Castro, and R. Benson, An electrically trainable artificial neural network (ETANN) with 10240 floating gate synapses, Proc. Int. Joint Conf. on Neural Networks, pp.II-191-196, June 1989.
9. O. Fujita and Y. Amemiya, A floating-gate analog memory device for neural networks, IEEE Trans. Electron Devices, vol.40, pp.2029-2035, 1993.
10. T. Kitaura, S. Sato, K. Nakajima, J. Murota, and Y. Sawada, Switched diffusion analog memory for neural networks, Ext. Abstracts of Int. Conf. on Solid State Devices and Materials, pp.449-451, 1993.
11. T. Shibata, H. Kosaka, H. Ishii, and T. Ohmi, A Neuron-MOS neural network using self-learningcompatible synapse circuits, IEEE J. Solid-State Circuits, vol.30, pp.913-922, 1995.
12. T. Morie, O. Fujita, and Y. Amemiya, Analog VLSI implementation of adaptive algorithms by an extended Hebbian synapse circuit, IEICE Trans. Electron., vol.E75-C, pp.303-311, 1992.
13. T. Morie, O. Fujita, and K. Uchimura, Self-learning neural network LSI with high-resolution non-volatile analog memory, IEEE Int. Conf. on Neural Networks, volume IV, pp.1628-1632, Perth, Nov. 1995.
14. R.C. Frye, E.A. Rietman, and C.C. Wong, Backpropagation learning and nonidealities in analog neural network hardware, IEEE Trans. Neural Networks, vol.2, pp.110-117, 1991.
15. T. Morie and Y. Amemiya, A study on high-precision analog neural network VLSI computers, IEICE Technical Report, ICD93-97/DSP93-58, 1993.