1 M synapse self-learning digital neural network chip

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 94-95,-421

  Saito, Osamu ^a   Aihara, Kimihisa ^a   Fujita, Osamu ^a   Uchimura, Kuniharu ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; LEARNING SYSTEMS; NEURAL NETWORKS; RANDOM ACCESS STORAGE;

DIGITAL NEURAL NETWORK CHIPS; SPARSE MEMORY ACCESS ARCHITECTURE (SMA);

MICROPROCESSOR CHIPS;

EID: 0031702317     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)