Required dynamic range and accuracy of electronic synapses for character recognition applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1992, Pages 1545-1548

  Lee, Bang W ^a   Kim, Sang W ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

LEARNING SYSTEMS; NEURAL NETWORKS; VLSI CIRCUITS;

DYNAMIC RANGE; EXCLUSIVE-OR; LEARNING PROCESS; NEURAL ARCHITECTURES; ON-CHIP LEARNING; PARITY CHECK; PROCESS STRATEGIES; SILICON TECHNOLOGIES;

CHARACTER RECOGNITION;

EID: 85027155548     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.1992.230204     Document Type: Conference Paper

References (10)

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3. J. E. Tomberg and K. K. K. Kaski, "Pulse-density modulation technique in VLSI implementations of neural network algorithms", IEEE Jour. of Solid-Slate Circuits, no. 5, vol. 25, pp. 1277-1286, Oct. 1990.
4. 80170NW Data Sheet, Intel Corporation, 1990.
5. T. Morishita, Y. Tamura, and T. Otsuki, "ABiCMOS analog neural network with dynamically updated weights", IEEE Inter. Solid-State Circuits Conf., pp. 142-143, San Francisco, CA., Feb. 1990.
6. D. W. Lcc and B. J. Sheu, "A compact and general-purpose neural chip with electrically programmable synapses", IEEE 1990 Custom Integrated Circuit Conf., p. 26.6.1, May, 1990.
7. B. W. Lee and B. J. Sheu, Hardware annealing in analog VLSI neurocomputing, Kluwer Academic Pub., 1991.
8. SU3232 and Nu32 Data Sheet, Intel Corporation, 1990.
9. M. S. Tomlinson, Jr., D. J. Walker, and M. A. Sivilotti, "A digital neural network architecture for VLSI", IEEE/INNS Inter. Joint Conf. on Neural Networks, vol. II, pp. 545-550, San Diego, CA., June 1990.
10. B. W. Lee and S. W. Kim, "Practical difficulties to design real-time learning VLSI neural circuits", 1991 IEEE/INNS Inter. Joint. Conf. on Neural Networks, Poster Presentation, July 1991.