A PWM signal processing core circuit based on a switched current integration technique

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 1, 1998, Pages 53-60

  Nagata, Makoto ^a,b,c,d   Funakoshi, Jun ^b,e   Iwata, Atsushi ^a,b,f,g,h,i  

^a IEEE   (Japan)

^b HIROSHIMA UNIVERSITY   (Japan)

^c GAKUSHUIN UNIVERSITY   (Japan)

^d IEICE ^*  (Japan)

^e Inst Electronics Info Commun E   (Japan)

^f NAGOYA UNIVERSITY   (Japan)

^g NTT CORPORATION   (Japan)

^h Institute of Electronics   (Japan)

ⁱ Far East Program Committee

Author keywords

Low power LSI design; Mixed analog digital integrated circuits; Pulse width modulation; PWM arithmetic; Switched current integrator; Time domain signal processing

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; DATA PROCESSING; DATA STORAGE EQUIPMENT; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATING CIRCUITS; LSI CIRCUITS; PULSE WIDTH MODULATION; TIME DOMAIN ANALYSIS;

ANALOG DIGITAL INTEGRATED CIRCUITS; LINEAR ARITHMETIC OPERATOR; SWITCHED CURRENT INTEGRATOR;

HYBRID INTEGRATED CIRCUITS;

EID: 0031672571     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.654937     Document Type: Article

References (13)

1. T. S. Fiez, G. Liang, and D. J. Allstot, "Switched-current circuit design issues," IEEE J. Solid-State Circuits, vol. 26, pp. 192-202, Mar. 1991.
2. J. B. Hughes and K. W. Moulding, "Switched-current signal processing for video frequencies and beyond," IEEE J. Solid-State Circuits, vol. 28, pp. 314-322, Mar. 1993.
3. _, "An 8 MHz, 80 Ms/s switched-current filter," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 60-61.
4. C. Toumazou, N. Pattersby, and S. Porta, Eds., Circuits and Systems Tutorials. Piscataway, NJ: IEEE Press, 1996, ch. 10.
5. A. Iwata and M. Nagata, "A concept of analog-digital merged circuit architecture for future VLSI's," IEICE Trans. Fundamentals, vol. E79-A, pp. 145-157, Feb. 1996.
6. A. F. Murray and A. V. W. Smith, "Asynchronous arithmetic for VLSI neural systems," Electron. Lett., vol. 23, no. 12, pp. 642-643, June, 1987.
7. J. E. Tomberg and K. K. K. Kaski, "Pulse-density modulation technique in VLSI implementations of neural network algorithms," IEEE J. Solid-State Circuits, vol. 25, pp. 1277-1286, Oct. 1990.
8. J. L. Meader, A. Wu, C. Cole, N. Nintunze, and P. Chintrakulchai, "Programmable impulse neural circuits," IEEE Trans. Neural Networks, vol. 2, pp. 101-109, Jan. 1991.
9. A. F. Murray, D. D. Corso, and L. Tarassenko, "Pulse-stream VLSI neural networks mixing analog and digital techniques," IEEE Trans. Neural Networks, vol. 2, pp. 193-204, Mar. 1991.
10. A. Hamilton, A. F. Murray, D. J. Baxter, S. Churcher, H. M. Reekie, and L. Tarassenko, "Integrated pulse stream neural networks: Results, issues, and pointers," IEEE Trans. Neural Networks, vol. 3, pp. 385-393, May 1992.
11. H. Inose and Y. Yasuda, "A unity bit coding method by negative feedback," Proc. IEEE, vol. 51, pp. 1524-1535, Nov. 1963.
12. K. Nogami and A. E. Gammel, "A CMOS 160 Mb/s phase modulation I/O interface circuit," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 108-109.
13. T. Yamaguchi, Y. Morooka, and H. Ozaki, "A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory," IEEE J. Solid-State Circuits, vol. 31, pp. 523-530, Apr. 1996.