Test sequences to achieve high defect coverage for synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 10, 1998, Pages 1017-1029

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

Defect coverage; Synchronous sequential circuits; Test generation

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING;

SYNCHRONOUS SEQUENTIAL CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0032184442     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.728921     Document Type: Article

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