Maple-opt: A performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGA's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 9, 1998, Pages 803-818

  Togawa, Nozomu ^a   Yanagisawa, Masao ^a   Ohtsuki, Tatsuo ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

Field programmable gate arrays (fpga's); Global routing; Placement; Technology mapping

Indexed keywords

ALGORITHMS; ELECTRIC DELAY LINES; FIELD PROGRAMMABLE GATE ARRAYS;

GLOBAL ROUTING ALGORITHM; TECHNOLOGY MAPPING;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032162446     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.720317     Document Type: Article

References (33)

1. N. B. Bhat and D. D. Hill, "Routable technology mapping for FPGA's," in P roc. IstACM/SIGDA Int. Workshop FPGA's (FPGA'92), Feb. 1992, pp. 143-148.
2. M. A. Breuer, "Min-cut placement," J. Design Automation Fault Tolerant Computing, vol. 1, no. 4, pp. 343-362, 1977.
3. S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, FieldProgrammable Gate Arrays. Norwell, MA: Kluwer, 1992.
4. S. Brown, J. Rose, and Z. G. Vranesic, "A detailed router for fieldprogrammable gate arrays," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 11, no. 5, pp. 620-628, 1992.
5. M. Burstein, S. J. Hong, and R. Pelavin, "Hierarchical VLSI layout: Simultaneous placement and wiring of gate arrays," in Proc. VLSI'83, 1983, pp. 45-60.
6. C.-S. Chen, Y.-W. Tsay, T. T. Hwang, A. C. H. Wu, and Y.-L. Lin, "Combining technology mapping and placement for delay-minimization in FPGA designs," IEEE Trans. Computer-Aided Design, vol. 14, no. 9, pp. 1076-1084, 1995.
7. J. Cong, Y. Ding, A. Kahng, P. Trajmar, and K. C. Chen, "An improved graph-based FPGA technology mapping for delay optimization," in Proc. 1992 IEEE Int. Conf. Comput. Design, 1992, pp. 154-158.
8. J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Trans. Computer-Aided Design, vol. 13, no. 1, pp. 1-12, 1994.
9. W.-M. Dai and E. S. Kuh, "Simultaneous floor planning and global routing for hierarchical building-block layout," IEEE Trans. Computer- Aided Design, vol. CAD-6, no. 5, pp. 828-837, 1987.
10. A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Juki, P. Kozak, and M. Wiesel, "Chip layout optimization using critical path weighting," in Proc. 21st DAC, 1984, pp. 133-136.
11. A. E. Dunlop and B. W. Kernighan, "A procedure for placement of standard-cell VLSI circuits," IEEE Trans. Computer-Aided Design, vol. CAD-4, no. 1, pp. 92-98, 1985.
12. R. J. Francis, J. Rose, and Z. Vranesic, "Chortle-erf: Fast technology mapping for lookup table-based FPGA's," in Proc. 28th DAC, 1991, pp. 227-233.
13. H.-C. Hsieh, W. S. Carter, J. Ja, E. Cheung, S. Schreifels, C. Erickson, P. Freidin, L. Tinkey, and R. Kanazawa, "Third-generation architecture boosts speed and density of field-programmable gate arrays," in Proc. IEEE 1990 Custom Integrated Circuits Conf., 1990, pp. 31.2.1-31.2.7.
14. K. Kawana, H. Keida, M. Sakamoto, K. Shibata, and I. Moriyama, "An efficient logic block interconnect architecture for user-reprogrammable gate array," in Proc. IEEE 1990 Custom Integrated Circuits Conf., 1990, pp. 31.3.1-31.3.4.
15. S. Kirkpatric, C. D. Gelatt, Jr., and M. P. Vecchi, "Optimization by simulated annealing," Science, vol. 220, no. 4598, pp. 671-680, 1983.
16. U. P. Lauther, "Top down hierarchical global routing for channelless gate arrays based on linear assignment," in Proc. VLSI'87, 1987, pp. 109-120.
17. R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. SangiovanniVincentelli, "Logic synthesis for programmable gate arrays," in Proc. 27th DAC, 1990, pp. 620-625.
18. R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Improved logic synthesis algorithms for table look up architectures," in Proc. ICCAD-91, 1991, pp. 564-567.
19. __, "Performance directed synthesis for table look up programmable gate arrays," in Proc. ICCAD-91, 1991, pp. 572-575.
20. S. K. Nag and R. A. Rutenbar, "Performance-driven simultaneous place and route for row-based FPGA's," in Proc. 31st DAC, 1994, pp. 301-307.
21. __, "Performance-driven simultaneous place and route for islandstyle FPGA's," in Proc. ICCAD-95, 1995, pp. 332-338.
22. Y. Ogawa, T. Ishii, Y. Shiraishi, H. Terai, T. Kozawa, K. Yuyama, and K. Chiba, "Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSI's," in Proc. 23rd DAC, 1986, pp. 404-410.
23. M. Ohmura, S. Wakabayashi, Y. Toyohara, J. Miyao, and N. Yoshida, "Hierarchical floorplanning and detailed global routing with routingbased partitioning," in Proc. ISCAS'90, 1990, pp. 1640-1643.
24. J. Rose and S. Brown, "Flexibility of interconnection structures for fieldprogrammable gate arrays," IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 277-282, 1991.
25. H. Sawada, T. Suyama, and A. Nagoya, "Logic synthesis for lookup table based FPGA's using functional decomposition and support minimization," in Proc. ICCAD-95, 1995, pp. 353-358.
26. M. Schlag, J. Kong, and P. K. Chan, "Routability-driven technolog mapping for lookup table-based FPGA's," IEEE Trans. Computer-Aide Design, vol. 13, no. 1, pp. 13-26, 1994.
27. P. R. Suaris and G. Kedem, "A quadrisection-based combined place an route scheme for standard cells," IEEE Trans. Computer-Aided Design vol. 8, no. 3, pp. 234-244, 1989.
28. R. E. Tarjan, Data Structures and Network Algorithms. Society fo Industrial and Applied Mathematics, 1983.
29. M. Terai, K. Takahashi, and K. Sato, "A new min-cut placement algorithm for timing assurance layout design meeting net length constraint, in Proc. 27th DAC, 1990, pp. 96-102.
30. N. Togawa, M. Sato, and T. Ohtsuki, "A simultaneous placement an global routing algorithm for FPGA's," in Proc. ISCAS'94, 1994, pp 483-486.
31. __, "Maple: A simultaneous technology mapping, placement, an global routing algorithm for field-programmable gate arrays," in Proc ICCAD-94, 1994, pp. 156-163.
32. S. Trimberger and M.-R. Chene, "Placement-based partitioning fo lookup-table-based FPGA's," in Proc. 1992 IEEE Int. Conf. Comput Design, 1992, pp. 91-94.
33. The Programmable Logic Data Book. Xilinx, 1994.