Efficient placement algorithms optimizing delay for high-speed ECL masterslice LST's

Proceedings - Design Automation Conference

Volumn , Issue , 1986, Pages 404-410

  Ogawa, Yasushi ^a   Ishii, Tatsuki ^a   Shiraishi, Yoichi ^a   Terai, Hidekazu ^a   Kozawa, Tokinori ^a   Yuyama, Kyoji ^b   Chiba, Kyoji ^a  

^a HITACHI LTD   (Japan)

^b Hitac Ltd ^*  (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; LSI CIRCUITS;

ELECTRICAL CHARACTERISTIC; EQUIVALENT CONSTRAINTS; IMPROVEMENT METHODS; ITERATIVE-WEIGHTED; MAINFRAME COMPUTER; PHYSICAL DESIGN; PLACEMENT ALGORITHM; TOP-DOWN METHODS;

ITERATIVE METHODS;

EID: 85027124733     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1986.1586121     Document Type: Conference Paper

References (11)

1. T. Kozawa, et al.; Automatic Placement Algorithms for High Packing Density VLSI, Proc. of 20th DA Conf., 1983.
2. H. Terai, et al.; Performance Analysis of Automatic Placement and Routing for Large-scale CMOS Masterslices, ICCD, 1983.
3. M. Burstein and M. N. Youssef, ; Timing Influenced Layout Design, Proc. of 22nd DA Conf., 1985.
4. A. E. Dunlop, et al.; Chip Layout Optimization Using Critical Path Weighting, Proc. of 21st DA Conf., 1984.
5. K.H. Khokhani, et al.; Placement of Variable Size Circuits On LSI Masterslices, Proc. of 18th DA Conf., 1981.
6. H. Terai, et al.; Automatic Placement and Routing Program for Logic VLSI Design based on Hierarchical layout Method, Proc. of Conf., ICCC, 1982.
7. M. Hanan, et al.; Placement Techniques, Chap. 5 in Design Automation of Digital Systems, Vol.1, Prentice-Hall, pp.213-282, 1972.
8. D. M. Schuler, et al.; Clustering and Linear Placement, Proc. of 9th DA Workshop, 1972.
9. B. Kernighan and S. Lin, ; An Efficient Heuristic for Partitioning Graphs, Bell System Technical Journal, Vol.49, 1982.
10. R. Kamikawai, et al.; Placement and Routing Program for Masterslice LSIs, Proc. of 13th DA Conf., 1976.
11. T. Kozawa, et al.; Advanced LILAC - an Automated Layout Generation System for MOS/LSIs, Proc. of 11th DA Conf., 1974.