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Volumn 26, Issue 3, 1991, Pages 277-282

Flexibility of Interconnection Structures for Field-Programmable Gate Arrays

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE;

EID: 0026124456     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.75006     Document Type: Article
Times cited : (140)

References (18)
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    • Rose, J.S.1    Francis, R.J.2    Chow, P.3    Lewis, D.4
  • 2
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  • 3
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  • 4
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    • May
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  • 5
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    • May
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  • 6
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    • Apr.
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    • El Gamal, A.1
  • 7
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    • May
    • M. Ahrens et al., “An FPGA family optimized for high densities and reduced routing delay,” in Proc. CICC, May 1990, pp. 31.5.1-31.5.4.
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  • 8
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    • A 5000-gate CMOS EPLD with multiple logic and interconnect arrays
    • May
    • S. C. Wong, H. C. So, J. H. Ou, and J. Costello, “A 5000-gate CMOS EPLD with multiple logic and interconnect arrays,” in Proc. CICC, May 1989, pp. 5.8.1-5.8.4.
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  • 10
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  • 11
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  • 12
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    • May
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  • 13
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.