-
1
-
-
21644489921
-
The effect of logic block complexity on area of programmable gate arrays
-
May
-
J. S. Rose, R. J. Francis, P. Chow, and D. Lewis, “The effect of logic block complexity on area of programmable gate arrays,” in Proc. CICC, May 1989, pp. 5.3.1-5.3.5.
-
(1989)
Proc. CICC
, pp. 5.3.1-5.3.5
-
-
Rose, J.S.1
Francis, R.J.2
Chow, P.3
Lewis, D.4
-
2
-
-
0025505369
-
Architecture of field-programmable gate arrays: The effect of logic block functionality on area efficiency
-
Oct.
-
J. S. Rose, R. J. Francis, D. Lewis, and P. Chow, “Architecture of field-programmable gate arrays: The effect of logic block functionality on area efficiency,” IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1217–1225, Oct. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, Issue.5
, pp. 1217-1225
-
-
Rose, J.S.1
Francis, R.J.2
Lewis, D.3
Chow, P.4
-
3
-
-
0022599035
-
A user programmable reconfigurable gate array
-
May
-
W. Carter et al., “A user programmable reconfigurable gate array,” in Proc. CICC, May 1986, pp. 233–235.
-
(1986)
Proc. CICC
, pp. 233-235
-
-
Carter, W.1
-
4
-
-
4243148198
-
A 9000-gate user-programmable gate array
-
May
-
H. Hsieh et al., “A 9000-gate user-programmable gate array,” in Proc. CICC, May 1988, pp. 15.3.1-15.3.7.
-
(1988)
Proc. CICC
, pp. 15.3.1-15.3.7
-
-
Hsieh, H.1
-
5
-
-
0025693998
-
Third-generation architecture boosts speed and density of field-programmable gate arrays
-
May
-
H. Hsieh et al., “Third-generation architecture boosts speed and density of field-programmable gate arrays,” in Proc. CICC, May 1990, pp. 31.2.1-31.2.7.
-
(1990)
Proc. CICC
, pp. 31.2.1-31.2.7
-
-
Hsieh, H.1
-
6
-
-
0024645788
-
An architecture for electrically configurable gate arrays
-
Apr.
-
A. El Gamal et al., “An architecture for electrically configurable gate arrays,” IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 394–398, Apr. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, Issue.2
, pp. 394-398
-
-
El Gamal, A.1
-
7
-
-
0025684074
-
An FPGA family optimized for high densities and reduced routing delay
-
May
-
M. Ahrens et al., “An FPGA family optimized for high densities and reduced routing delay,” in Proc. CICC, May 1990, pp. 31.5.1-31.5.4.
-
(1990)
Proc. CICC
, pp. 31.5.1-31.5.4
-
-
Ahrens, M.1
-
8
-
-
0024665580
-
A 5000-gate CMOS EPLD with multiple logic and interconnect arrays
-
May
-
S. C. Wong, H. C. So, J. H. Ou, and J. Costello, “A 5000-gate CMOS EPLD with multiple logic and interconnect arrays,” in Proc. CICC, May 1989, pp. 5.8.1-5.8.4.
-
(1989)
Proc. CICC
, pp. 5.8.1-5.8.4
-
-
Wong, S.C.1
So, H.C.2
Ou, J.H.3
Costello, J.4
-
10
-
-
84939320166
-
Logic array beats development time blues
-
Nov.
-
C. Marr, “Logic array beats development time blues,” Electron. Syst. Des. Mag., pp. 38–42, Nov. 1989.
-
(1989)
Electron. Syst. Des. Mag
, pp. 38-42
-
-
Marr, C.1
-
11
-
-
0025626649
-
An efficient logic block interconnect architecture for user-programmable gate array
-
May
-
K. Kawana et al., “An efficient logic block interconnect architecture for user-programmable gate array,” in Proc. CICC, May 1990, pp. 31.3.1-31.3.4.
-
(1990)
Proc. CICC
, pp. 31.3.1-31.3.4
-
-
Kawana, K.1
-
12
-
-
0025682809
-
The effect of switch box flexibility on routability of field programmable gate arrays
-
May
-
J. S. Rose and S. Brown “The effect of switch box flexibility on routability of field programmable gate arrays,” in Proc. CICC, May 1990, pp. 27.5.1-27.5.4.
-
(1990)
Proc. CICC
, pp. 27.5.1-27.5.4
-
-
Rose, J.S.1
Brown, S.2
-
14
-
-
0023210698
-
DAGON: Technology binding and local optimization by DAG matching
-
June
-
K. Keutzer, “DAGON: Technology binding and local optimization by DAG matching,” in Proc. 24th Design Automation Conf., June 1987, pp. 341–347.
-
(1987)
Proc. 24th Design Automation Conf
, pp. 341-347
-
-
Keutzer, K.1
-
15
-
-
0025532128
-
Chortle: A technology mapping program for lookup table-based field programmable gate arrays
-
June
-
R. J. Francis, J. Rose, and K. Chung, “Chortle: A technology mapping program for lookup table-based field programmable gate arrays,” in Proc. 27th Design Automation Conf., June 1990, pp. 613–619.
-
(1990)
Proc. 27th Design Automation Conf
, pp. 613-619
-
-
Francis, R.J.1
Rose, J.2
Chung, K.3
-
16
-
-
0003165860
-
ALTOR: An automatic standard cell layout program
-
Nov.
-
J. Rose, Z. Vranesic, and W. M. Snelgrove, “ALTOR: An automatic standard cell layout program,” in Proc. Can. Conf. VLSI, Nov. 1985, pp. 168–173.
-
(1985)
Proc. Can. Conf. VLSI
, pp. 168-173
-
-
Rose, J.1
Vranesic, Z.2
Snelgrove, W.M.3
-
17
-
-
0024133780
-
LocusRoute: A parallel global router for standard cells
-
June
-
J. Rose, “LocusRoute: A parallel global router for standard cells,” in Proc. 25th Design Automation Conf., June 1988, pp. 189–195.
-
(1988)
Proc. 25th Design Automation Conf
, pp. 189-195
-
-
Rose, J.1
|