CHIP LAYOUT OPTIMIZATION USING CRITICAL PATH WEIGHTING.

Proceedings - Design Automation Conference

Volumn , Issue , 1984, Pages 133-136

  Dunlop, A E ^a   Agrawal, V D ^a   Deutsch, D N ^a   Jukl, M F ^a   Kozak, P ^a   Wiesel, M ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CHIP LAYOUT; CRITICAL PATH WEIGHTING; CRITICAL TIMING PATHS; OPTIMIZATION; PATH ANALYSIS DATA; ROUTING;

INTEGRATED CIRCUITS;

EID: 0021212391     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.1984.1585786     Document Type: Conference Paper

References (0)