Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 353-358

  Sawada, Hiroshi ^a   Suyama, Takayuki ^a   Nagoya, Akira ^a  

^a NTT Communication Science Laboratories   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; ELECTRIC NETWORK SYNTHESIS; GRAPH THEORY; LOGIC DESIGN; TABLE LOOKUP;

BINARY DECISION DIAGRAMS (BDD); BOOLEAN RESUBSTITUTION TECHNIQUE; FUNCTIONAL DECOMPOSITION; LOGIC SYNTHESIS; SUPPORT MINIMIZATION;

LOGIC GATES;

EID: 0029510039     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)