An efficient logic block interconnect architecture for user-reprogrammable gate array

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1990, Pages

  Kawana, Keiichi ^a   Keida, Hisaya ^a   Sakamoto, Makoto ^a   Shibata, Keiji ^a   Moriyama, Ichiro ^a  

^a JFE STEEL CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, CMOS--DESIGN; LOGIC DEVICES--DESIGN;

LOGIC BLOCK INTERCONNECT ARCHITECTURE; PROGRAMMABLE LOGIC ELEMENTS; SRAMS; USER REPROGRAMMABLE GATE ARRAY;

DATA STORAGE, DIGITAL;

EID: 0025626649     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)