Single-Event Charge Enhancement in SOI Devices

IEEE Electron Device Letters

Volumn 11, Issue 2, 1990, Pages 98-99

  Massengill, Lloyd W ^a   Kerns, David V ^a   Kerns, Sherra E ^a   Alles, M L ^a  

^a VANDERBILT UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

IONS; PHOTOELECTRICITY; SEMICONDUCTING SILICON;

CHARGE ENHANCEMENT; CMOS TECHNOLOGY; SILICON-ON-INSULATOR DEVICES;

SEMICONDUCTOR DEVICES, MOS;

EID: 0025386531     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.46941     Document Type: Article

References (5)

1. S. S. Eaton and B. Lalevic, “The effect of a floating substrate on the operation of silicon-on-sapphire transistors,” IEEE Trans. Electron Devices, vol. ED-25, pp. 907–912, Aug. 1978.
2. J. Tihanyi and H. Schlotterer, “Properties of ESFI MOS transistors due to the floating substrate and the finite volume,” IEEE Trans. Electron Devices, vol. ED-22, pp. 1017–1023, Nov. 1975.
3. S. E. Diehl, A. Ochoa, P. V. Dressendorfer, R. Koga, and W. A. Kolasinski, “Error analysis and prevention of cosmic ion induced soft errors in static CMOS RAMs,” IEEE Trans. Nucl. Sci., vol. NS-29, no. 6, pp. 2032–2039, Dec. 1982.
4. J. P. Colinge, “An SOI voltage-controlled bipolar-MOS device,” IEEE Trans. Electron Devices, vol. ED-34, pp. 845–849, Apr. 1987.
5. D. K. Nichols, W. E. Price, and C. J. Malone, “Single event upset (SEU) of semiconductor devices,” IEEE Trans. Nucl. Sci., vol. NS-30, no. 6, pp. 4520–4525, Dec. 1983.