A mathematical basis for power-reduction in digital vlsi systems

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 11, 1997, Pages 935-951

  Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Digital CMOS; Information theory; Low power

Indexed keywords

ALGORITHMS; CHANNEL CAPACITY; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; INFORMATION THEORY; NUMERICAL ANALYSIS;

INFORMATION TRANSFER RATE; POWER REDUCTION;

VLSI CIRCUITS;

EID: 0031269121     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.644047     Document Type: Article

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