Optimal Interconnection Circuits for VLSI

IEEE Transactions on Electron Devices

Volumn 32, Issue 5, 1985, Pages 903-909

  Bakoglu, H B ^a   Meindl, James D ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING - OPTIMIZATION; SEMICONDUCTOR DEVICES, MOSFET - APPLICATIONS;

INTERCONNECTION LINES; PROPAGATION DELAY;

INTEGRATED CIRCUITS, VLSI;

EID: 0022061669     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1985.22046     Document Type: Article

References (27)

1. A. J. Blodgett, “Microelectronic packaging,” Sci. Amer., pp. 86–96, 96, July 1983.
2. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion implanted MOSFET's with very small physcial dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp, 256–268, Oct. 1974.
3. VLSI Laboratory, Texas Instruments Inc., “Technology and design challenges of MOS VLSI,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 442–448, June 1982.
4. K. C. Saraswat and F. Mohammadi, “Effect of scaling of interconnections on the time delay of VLSI circuits,” IEEE J. Solid-State State Circuits, vol. SC-17, pp. 275–280, Apr. 1982.
5. P. M. Solomon, “A comparison of semiconductor devices for high speed logic,” Proc. IEEE, vol. 70, pp. 489–509, May 1982.
6. H. Yuan, Y. Lin, and S. Chiang, “Properties of interconnection on silicon, sapphire, and semi-insulating gallium arsenide substrates,” IEEE Trans. Electron Devices, vol. ED-29, pp. 639–644, 644, Apr. 1982.
7. T. Sakurai and T. Tamaru, “Simple formulas for two and three-dimensional dimensional capacitances,” IEEE Trans. Electron Devices, vol. ED-30, pp. 183–185, Feb. 1983.
8. A. E. Ruehli, “Survey of computer-aided electrical analysis of intergrated circuit interconnections,” IBM J. Res. Develop., vol. 23, pp. 626–639, Nov. 1979.
9. A. E. Ruehli and P. A. Brennan, “Accurate metallization capacitances for integrated circuits and packages,” IEEE J. Solid-State Circuits, vol. SC-8, pp. 289–290, Aug. 1973.
10. A. E. Ruehli andx P. A. Brennan, “Capacitance models for integrated circuit metallization wires,” IEEE J. Solid-State Circuits, vol. SC-10, Dec. 1975.
11. R. L. M. Dang and N. Shigyo, “Coupling capacitances for two-dimensional dimensional wires,” IEEE Electron Device Lett., vol. EDL-2, pp. 196–197, Aug. 1981.
12. W. H. Chang, “Analytical IC metal-line capacitance formulas,” IEEE Trans. Microwave Theory Tech., vol. MTT-24, pp. 608–611, 611, Sept. 1976.
13. D. B. Scott, W. R. Hunter, and H. Shichijo, “A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits,” IEEE Trans. Electron Devices, vol. ED-29, pp. 651–661, Apr, 1982.
14. A. K. Sinha, J. A. Cooper, and H. J. Levinstein, “Speed limitations due to interconnect time constants in VLSI integrated circuits,” IEEE Electron Device Lett., vol. EDL-3, pp. 90–92, Apr. 1982.
15. A. Mayadas and M. Sahtzkes, “Electrical resistivity model for polycrystalline films: The case of arbitrary reflection at external surface,” Phys. Rev., B-1, pp. 1382-1389, 1970.
16. A. Wilnai, “Open-ended RC line model predicts MOSFET IC response,” EDN, pp. 53–54, Dec. 1971.
17. T. Sakurai, “Approximation of wiring delay in MOSFET LSI,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 418–426, Aug. 1983.
18. H. B. Bakoglu and J. D. Meindl, “Optimal interconnect circuits for VLSI,” in ISSCC Dig. Tech. Papers, pp. 164–165, Feb. 1984.
19. R. W. Keyes, “The wire-limited logic chip,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1232–1233, Dec. 1982.
20. C. Mead and M. Rem, “Minimum propagation delays in VLSI,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 773–775, Aug. 1982.
21. P. I. Suciu and R. L. Johnson, “Experimental derivation of the source and drain resistance of MOS transistors,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1846–1848, Sept. 1980.
22. C. Y. Chang, Y. K. Fang, and S. M. Sze, “Specific contact resistance of metal-semiconductor barriers,” Solid-State Electron., vol. 14, p. 541, 1971.
23. D. Pramanik and A. N. Saxena, “VLSI metallization using aluminum and its alloys: Part I,” Solid State Technol., pp. 127–133, 133, Jan. 1983.
24. D. Pramanik and A. N. Saxena, “VLSI metallization using aluminum and its alloys: Part II,” Solid State Technol., pp. 131–138, Mar. 1983.
25. C. L. Seitz, “Self-timed VLSI systems,” in Proc. Caltech Conf. VLSI, C. L. Seitz, 345–355, Jan. 1980.
26. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, ch. 7.
27. R. W. Keyes, “The evolution of digital electronics towards VLSI,” IEEE Trans. Electron Devices, vol. ED-26, pp. 271-278, 1979.