Impact of polysilicon emitter interfacial layer engineering on the 1/f noise of bipolar transistors

IEEE Transactions on Electron Devices

Volumn 43, Issue 12, 1996, Pages 2261-2268

  Simoen, Eddy ^a   Decoutere, Stefaan ^a   Cuthbertson, Alan ^a   Claeys, Cor L ^a   Deferm, Ludo ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; DRY ETCHING; ELECTRIC CURRENTS; INTEGRATED CIRCUIT MANUFACTURE; OXIDES; SEMICONDUCTOR DEVICE MANUFACTURE; SPURIOUS SIGNAL NOISE;

CURRENT GAIN; EMITTER BASE JUNCTION DEPTH; EMITTER RESISTANCE; POLYSILICON EMITTER INTERFACE ENGINEERING;

BIPOLAR TRANSISTORS;

EID: 0030391897     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.544419     Document Type: Article

References (15)

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