A 200MHz 64b dual-issue CMOS microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 1992-February, Issue , 1992, Pages 106-107

  Dobberpuhl, Daniel ^a   Witek, Richard ^a   Allmon, Randy ^a   Anglin, Robert ^a   Britton, Sharon ^a   Chao, Linda ^a   Conrad, Robert ^a   Dever, Daniel ^a   Gieseke, Bruce ^a   Hoeppner, Gregory ^a   Kowaleski, John ^a   Kuchler, Kathryn ^a   Ladd, Maureen ^a   Leary, Michael ^a   Madden, Liam ^a   McLellan, Edward ^a   Meyer, Derrick ^a   Montanaro, James ^a   Priore, Donald ^a   Rajagopalan, Vidya ^a   Samudrala, Sridhar ^a   Santhanam, Sribalan ^a   more..

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; PROGRAMMED CONTROL SYSTEMS;

CLOCK CYCLES; EXECUTION UNITS; FLOATING POINT UNITS; FULLY PIPELINED; LINEAR ADDRESS SPACE; REDUCED INSTRUCTION SET COMPUTERS; REGISTER FILES; THREE-LAYER;

PIPELINES;

EID: 33747946662     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1992.200434     Document Type: Conference Paper

References (3)

1. Conrad, R., et. al., "A 50 MIPS (Peak) 32/64b Microprocessor". ISSCC DIGEST OF TECHNICAL PAPERS, pp. 76-7. Feb., 1989.
2. Sklansky, J., "Conditional-Sum Addition Logic", IRE Trans. Electron. Comput. EC-9, pp. 226-231, 1960.
3. Lee, H., et. al., "An Experimental 1Mb CMOS SRAM with Configurable Organization and Operation", ISSCC DIGEST OF TECHNICAL PAPERS, pp. 180-181, Feb., 1988.