Zero-skew clock routing scheme for VLSI circuits

IEEE/ACM International Conference on Computer-Aided Design

Volumn , Issue , 1992, Pages 458-463

  Li, Ying Meng ^a   Jabri, Marwan A ^a  

^a UNIVERSITY OF SYDNEY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DELAY CIRCUITS; ELECTRIC LINES; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; TREES (MATHEMATICS);

BUILDING BLOCK LAYOUT; CLOCK ROUTING SCHEME; CLOCK WIRE LENGTH; TIME COMPLEXITY; VORONOI DIAGRAM; ZERO SKEW ROUTING;

VLSI CIRCUITS;

EID: 0027002266     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)