Planar clock routing for high performance chip and package co-design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 4, Issue 2, 1996, Pages 210-226

  Zhu, Qing ^a,b   Dai, Wayne Wei Ming ^a,c  

^a IEEE

^b INTEL CORPORATION   (United States)

^c University of California Santa Cruz   (United States)

Author keywords

Chip and package co design; Clock distribution; Clock routing; Clock tree; Flip chip; Interconnect; Package; Planar routing; Steiner tree

Indexed keywords

ALGORITHMS; FLIP CHIP DEVICES; GEOMETRY; INTEGRATED CIRCUIT LAYOUT; TIMING CIRCUITS; TREES (MATHEMATICS);

CLOCK DISTRIBUTION; CLOCK DRIVER; CLOCK NETWORK; CLOCK TREE; GEOMETRIC EMBEDDING METHOD; HIGH PERFORMANCE CHIP; PACKAGE CODE SIGN; PLANAR CLOCK RATING; PLANAR ROUTING; STEINER TREE;

VLSI CIRCUITS;

EID: 0030166489     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.502193     Document Type: Article

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