Redesign technique for combinational circuits based on gate reconnections

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 632-637

  Kukimoto, Yuji ^a   Fujita, Masahiro ^a   Brayton, Robert K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ARRAYS; BOOLEAN ALGEBRA; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; LOGIC GATES; MODIFICATION; TECHNOLOGY;

GATE ARRAY; GATE RECONNECTIONS; REDESIGN TECHNIQUE; STANDARD CELL TECHNOLOGY;

COMBINATORIAL CIRCUITS;

EID: 0028724606     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)