Diagnosis oriented test pattern generation

Proceedings of the European Design Automation Conference, EDAC 1990

Volumn , Issue , 1990, Pages 470-474

  Camurati, P ^a   Lioy, A ^a   Prinetto, P ^a   Sonza Reorda, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

DIAGNOSTIC CAPABILITIES; TEST PATTERN; TEST PATTERN GENERATIONS;

AUTOMATIC TEST PATTERN GENERATION;

EID: 38749131846     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDAC.1990.136693     Document Type: Conference Paper

References (8)

1. P. Camurati, A. Lioy, P. Prinetto, M. Sonza Reorda: "The Diagnosis of Digital Circuits, " Politecnico di Torino-D.A.I.-Internal Report CAD15/89
2. J.P. Roth, W.G. Bouricius, P.R. Schneider: "Programmed Algorithms to Compute Tests to Detect and Distinguish between Failures in Logic Circuits, " IEEE Trans, on Electronic Computers, Vol. EC-16, No. 5, Oct. 1967, pp. 567-580
3. J. Savir, J.P. Roth: "Testing for., Distinguishing Between Failures, " FTCS-12: 12th Fault Tolerant Computing Symp., Santa Monica, (CA), June 22-24, 1982, pp. 165-172
4. P. Goel: "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits, " IEEE Trans, on Computers, Vol. C-30, No. 3, Mar. 1981, pp. 215-222
5. H. Fujiwara, T. Shimono: "On The Acceleration of Test Generation Algorithms, " IEEE Trans, on Computers, Vol. C-32, No. 12, Dec. 1983, pp. 1137-1144
6. P. Goel, B.C. Rosales: "Podem-X: An Automatic Test Generation System for VLSI Logic Structures, " DAC-18: 18th IEEE/ACM Design Automation Conf., Nashville, (TE), June 1981, pp. 260-268
7. F. Brglez, H. Fujiwara: "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran, " ISCAS-85: IEEE Int. Symp. on Circuits And Systems, Vol. 3 of 3, Kyoto (Japan), June 1985
8. K.To, "Fault Folding for Irredundant and Redundant Combinational Circuits, " IEEE Trans, on Computers, Vol. C-22, No. 11, Nov. 1973, pp. 1008-1015