Compact multiple-valued multiplexers using negative differential resistance devices

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 8, 1996, Pages 1151-1155

  Chan, H L ^b,c,e,f   Mohan, S ^a,b,d,f,g   Mazumder, Pinaki ^{a,b,h,i,j,k,l,m,n}   Haddad, George I ^a,b  

^a IEEE

^b University of Michigan   (United States)

^c CYPRESS SEMICONDUCTOR   (United States)

^d XILINX INC   (United States)

^e UNIVERSITY OF ARIZONA   (United States)

^f UNIVERSITY OF MICHIGAN   (United States)

^g INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

^h INDIAN INSTITUTE OF SCIENCE   (India)

ⁱ UNIVERSITY OF ALBERTA   (Canada)

^j UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^k University of Illinois at Urbana Champaign   (United States)

^l BHARAT ELECTRONICS LIMITED   (India)

^m LUCENT TECHNOLOGIES   (United States)

ⁿ ACM SIGDA

more..

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); HIGH ELECTRON MOBILITY TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; NEGATIVE RESISTANCE; QUANTUM ELECTRONICS; SEMICONDUCTOR DIODES;

MULTIPLE VALUED MULTIPLEXERS; NEGATIVE DIFFERENTIAL RESISTANCE;

MULTIPLEXING EQUIPMENT;

EID: 0030211846     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508262     Document Type: Article

References (13)

1. F. Capasso, S. Sen, F. Beltram, L. M. Lunardi, A. S. Vengurlekar, P. R. Smith, N. J. Shah, R. J. Malik, and A. Y. Cho, "Quantum functional devices: Resonant-tunneling transistors, circuits with reduced complexity and multiple-valued logic," IEEE Trans. Electron Devices, vol. 36, pp. 2065-2082, Oct. 1989.
2. L. L. Chang, L. Esaki, and R. Tsu, "Resonant tunneling in semiconductor double barriers," Appl. Physics Lett., vol. 24, pp. 593-595, 1974.
3. S. L. Hurst, "Two decades of multiple-valued logic - An invited tutorial," in Proc. 20th Int. Symp. Multiple-Valued Logic, 1988, pp. 164-175.
4. F. Capasso, S. Sen, A. Y. Cho, and D. Sivco, "Resonant tunneling devices with multiple negative differential resistance and demonstration of a three-state memory cell for multiple-valued logic applications," IEEE Electron Device Lett., vol. EDL-8, July 1987.
5. A. Sellai, M. S. Raven, D. P. Steenson, J. M. Chamberlain, M. Henini, and O. M. Hughes, "Double-barrier resonant tunneling diode three-state logic," Electron. Lett., vol. 26, pp. 61-62, Jan. 1990.
6. S.-J. Wei and H. C. Lin, "Multivalued SRAM cell using resonant tunneling diodes," IEEE J. Solid-State Circuits, vol. 27, pp. 212-216, Feb. 1992.
7. L. J. Micheel and M. J. Paulus, "Differential multiple-valued logic using resonant tunneling diodes," in IEEE 20th Int. Symp. Multiple-Valued Logic, 1990, pp. 189-195.
8. D. C. Rine, Computer Science and Multiple-Valued Logic Theory and Applications. Amsterdam, The Netherlands: North-Holland, 1984.
9. P. Mazumder, J. P. Sun, S. Mohan, and G. I. Haddad, "DC and transient simulation of resonant tunneling devices in NDR-SPICE," in 21st Int. Symp. Compound Semiconductors, 1994.
10. W. L. Chen, G. O. Munns, D. Knightly, J. R. East, and G. I. Haddad, "InGaAs/AlAs/InGaAsP RTBT grown by CBE," in Proc. IEEE/Cornell Conf. Advanced Concepts in High Speed Semiconductor Devices and Circuits, Aug. 1993, p. 290.
11. W. L. Chen, G. O. Munns, J. R. East, and G. I. Haddad, "InGaAs/AlAs/InGaAsP resonant tunneling hot electron transistors grown by chemical beam epitaxy," IEEE Trans. Electronic Devices, vol. 41, no. 2, pp. 155-161, Feb. 1994.
12. M. Abe and N. Yokoyama, Semiconductor Heterostructure Devices. New York: Gordonand Breach, 1989.
13. J. F. Whitaker, G. A. Mourou, T. C. L. G. Sollner, and W. D. Goodhue, "Picosecond switching-time measurement of a resonant-tunneling diode," Appl. Physics Lett., vol. 53, pp. 385-387, Aug. 1988.