A scalable system architecture for high-throughput turbo-decoders

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 39, Issue 1-2 SPEC.ISS., 2005, Pages 63-77

  Thul, Michael J ^a   Gilbert, Frank ^a   Vogt, Timo ^a   Kreiselmaier, Gerd ^a   Wehn, Norbert ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

High throughput; Interleaving; Parallel decoding; Turbo Decoder; VLSI architectures; Wireless

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DECODING; INPUT OUTPUT PROGRAMS; PROBABILITY; THROUGHPUT; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

HIGH-THROUGHPUT; INTERLEAVING; PARALLEL DECODING; TURBO-DECODERS;

COMPUTER ARCHITECTURE;

EID: 9144240002     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:VLSI.0000047272.75049.0e     Document Type: Conference Paper

References (27)

1. C. Berrou, A. Glavieux, and P. Thilimajshima, "Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes," in Proc: 1993 International Conference on Communications (ICC '93), Geneva, Switzerland, 1993, pp. 1064-1070.
2. Third Generation Partnership Project. 3GPP home page. www.3gpp.org.
3. H. Dawid, G. Gehnen, and H. Meyr, "MAP Channel Decoding: Algorithm and VLSI Architecture," in VLSI Signal Processing VI. IEEE, 1993, pp. 141-149.
4. A. Worm, H. Lamm, and N. Wenn, "Design of Low-Power High-Speed Maximum a Posteriori Decoder Architectures," in Proc. 2001 Design, Automation unit Test in Europe (DATE '01), Munich, Germany, 2001, pp. 258-265.
5. T. Richter and G. Fettweis, "Parallel Interleaving on Parallel DSP Architectures," in Proc. 2002 Workshop on Signal Processing Systems (SiPS '02), 2002, pp. 195-200.
6. R. Dobkin, M. Peleg, and R. Ginosur, "Parallel VLSI Architecture for Map Turbo Decoder," in 13th International Symposium on Personal, Indoor and Mobile Radio Communications 2002, 2002. vol, 1. pp. 384-388.
7. A. Giulietti, L. van der Perre, and M. Strum, "Parallel Turbo Decoding Interleavers: Avoiding Collisions in Accesses to Storage Elements," Electronics Letters, vol. 38, no. 5, 2002, pp. 232-234.
8. M.J. Thul, N. Wehn, and L.P. Rao, "Enabling High-Speed Turbo-Decoding Through Concurrent Interleaving," in Proc. 2002 IEEE International Symposium on Circuits and Systems (ISCAS '02), Phoenix, Arizona, USA, 2002, pp. 897-900.
9. D. Sylvester and K. Keutzer, "Rethinking Deep-Submicron Circuit Design," IEEE Computer, vol. 32, no. 11, 1999, pp. 25-33
10. J. Vogt, K. Koora, A. Finger, and G. Fettweis, "Comparison of Different Turbo Decoder Realizations for IMT-2000," in Proc. 1999 Global Telecommunications Conference (Globecom '99), Rio de Janeiro, Brazil, 1999, vol. 5, pp. 2704-2708.
11. F. Gilbert, F. Kienle, and N. Wehn, "Low Complexity Stopping Criteria for UMTS Turbo-Decoders," in Proc. 2003-Spring Vehicular Technology Confernce (VTC Spring '03), Jeju, Korea, 2003.
12. P. Robertson, P. Hoeher, and E. Villebrun, "Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding," European Transactions on Telecommunications (ETT), vol. 8, no. 2, 1997, pp. 119-125.
13. F. Kienle, H. Michel, F. Gilbert, and N. Wehn, "Efficient MAP-Algorithm Implementation on Programmable Architectures," in Kleinheubacher Berichte 2003, Miltenberg, Germany, vol. 46, 2002, to appear.
14. M.J. Thul, F. Gilbert, T. Vogt, G. Kreiselmaier, and N. Wehn, "A Scalable System Architecture for High-Throughput Turbo-Decoders," in Proc. 2002 Workshop on Signal Processing Systems (SiPS '02), San Diego, California, USA, 2002, pp. 152-158.
15. A. Worm, "Implementation Issues of Turbo-Decoders" PhD Thesis, Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern, ISBN 3-925178-72-4, 2001.
16. C. Schurgers, M. Engels, and F. Catthoor, "Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module," in Proc. 1999 International Symposium on Low Power Electronics and Design (ISLPED '99), San Diego, California, USA, 1999, pp. 76-81.
17. Z. Wang, H. Suzuki, and K.K. Parhi, "VLSI Implementation Issues of Turbo Decoder Design for Wireless Applications," in Proc. 1999 Workshop in Signal Processing Systems (SiPS '99), Taipei, Taiwan ROC, 1999, pp. 503-512.
18. A. Worm, H. Michel, F. Gilbert, G. Kreiselmaier, M.J. Thul, and N. Wehn, "Advanced Implementation Issues of Turbo-Decoders," in Proc. 2nd International Symposium on Turbo Codes & Related Topics, Brest, France, 2000, pp. 351-354.
19. Z. Wang, Z. Chi, and K. Parhi, "Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders," in Proc. 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '01), Salt Lake City, UT, USA, vol. 4, 2001, pp. 2633-2636.
20. T. Miyauchi, K. Yamamoto, T. Yokokawa, M. Kan, Y. Mizutani, and M. Hattori, "High-Performance Programmable SISO Decoder VLSI Implementation for Decoding Turbo Codes," in Global Telecommunications Conference, 2001 (GLOBECOM '01), San Antonio, TX, USA, vol. 1, 2001, pp. 305-309.
21. A. Giulietti, B. Bougard, V. Derudder, S. Dupont, J.-W. Weijers, and L. van der Perre, "A 80 Mb/s Low-Power Scalable Turbo Codec Core," in Custom Integrated Circuits Conference (CICC) 2002, Orlando, Florida, USA, 2002, pp. 389-392.
22. S. Crozier, "New High-Spread High-Distance Interleavers for Turbo-Codes," in Proc. 20-th biennal Symposium on Communications, Kingston, Canada, 2000, pp. 3-7.
23. M.J. Thul, F. Gilbert, and N. Wehn, "Optimized Concurrent Interleaving for High-Throughput Turbo-Decoding," in Proc. 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS '02), Dubrovnik, Croatia, 2002, pp. 1099-1102.
24. P. Pirsch, Architectures for Digital Signal Processing, John Wiley & Sons, Inc., 1998.
25. L. Benini and G.D. Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computer, vol. 35, no. 1, 2002, pp. 70-78.
26. C. Schurgers, F. Catthoor, and M. Engels, "Optimized MAP Turbo Decoder," in Proc. 2000 Workshop on Signal Processing Systems (SiPS '00), Lafayette, Louisiana, USA, 2000, pp. 245-254.
27. M.J. Thul, F. Gilbert, and N. Wehn, "Concurrent Interleaving Architectures for High-Throughput Channel Coding," in Proc. 2003 Conference on Acoustics, Speech, and Signal Processing (ICASSP -031, Hong Kong, P.R.China, 2003.