Area-efficient high speed decoding schemes for turbo/map decoders

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 4, Issue , 2001, Pages 2633-2636

  Wang, Zhongfeng ^a   Chi, Zhipei ^b   Parhi, Keshab K ^b  

^a Infineon Technologies MorphICs Inc   (United States)

^b University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; PARALLEL PROCESSING SYSTEMS; TURBO CODES;

PARALLELISM; PIPELINE-INTERLEAVING TECHNIQUE;

DECODING;

EID: 0034854846     PISSN: 15206149     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICASSP.2001.940542     Document Type: Article

References (9)

1. Near Shannon limit error-correcting coding and decoding: Turbo codes
2. A parallel decoding scheme for turbo codes
3. A high-speed map architecture with optimized memory size and power consumption
4. An intuitive justification of the MAP decoder for convolutional codes
5. VLSI implementation issues of turbo decoder design for wireless applications
6. A K = 3, 2 Mbps low power turbo decoder for 3rd generation W-CDMA systems
7. High performance, low complexity VLSI design of turbo decoders
8. Pipeline interleaving and parallelism in recursive digital filters-part I: Pipelining using scattered look-ahead and decomposition