A 2Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 66-67+432

  Zerbe, J L ^a   Chau, P S ^a   Werner, C W ^a   Stonecypher, W F ^a   Liaw, H J ^a   Gong Jong Yeh, ^a   Thrush, T P ^a   Best, S C ^a   Donnelly, K S ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; DIGITAL SIGNAL PROCESSING; EQUALIZERS; MICROPROCESSOR CHIPS; PULSE AMPLITUDE MODULATION;

CROSS-TALK CANCELLATION (XTC); SELF-EQUALIZATION (EQS);

DATA COMMUNICATION SYSTEMS;

EID: 0035054709     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. 1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus
2. A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver
3. GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link
4. A 2.4Gb/s per-pin simultaneous bidirectional parallel link with per-pin skew calibration
5. A 700-Mb/s/pin CMOS signaling interface using current integrating receivers