An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 492-494

  Ihm, Jeong Don ^a   Bae, Seung Jun ^a   Park, Kwang Il ^a   Song, Ho Young ^a   Lee, Woo Jin ^a   Kim, Hyun Jin ^a   Kim, Kyung Ho ^a   Lee, Ho Kyung ^a   Park, Min Sang ^a   Bang, Sam Young ^a   Lee, Mi Jin ^a   Moon, Gil Shin ^a   Jang, Young Wook ^a   Hwang, Suk Won ^a   Cho, Young Chul ^a   Hwang, Sang Jun ^a   Kim, Dae Hyun ^a   Lim, Ji Hoon ^a   Kim, Jae Sung ^a   Park, Su Jin ^a   Park, Ok Joo ^a   Yang, Se Mi ^a   Choi, Jin Yong ^a   Kim, Young Wook ^a   Lee, Hyun Kyu ^a   Kim, Sung Hoon ^a   Jang, Seong Jin ^a   Jun, Young Hyun ^a   Cho, Soo In ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; ELECTRIC POWER UTILIZATION; ENCODING (SYMBOLS); FREQUENCY MODULATION; VOLTAGE CONTROL;

DATA-BUS INVERSION CODING; DUTY-CYCLE CORRECTORS; SDRAM; VOLTAGE FLUCTUATION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 34548861237     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373509     Document Type: Conference Paper

References (6)

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2. Graphics Double Data Rate 4 (GDDR4) SGRAM Specification, JEDEC.
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