A 500MHz DLL with second order duty cycle corrector for low jitter

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 325-328

  Kim, Byung Guk ^a   Oh, Kwang Il ^a   Kim, Lee Sup ^a   Lee, Dae Woo ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; LOW PASS FILTERS;

EXTERNAL INPUT DUTY ERRORS; LOOP STABILITY; SECOND ORDER DUTY CYCLE CORRECTORS;

JITTER;

EID: 33847110289     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568671     Document Type: Conference Paper

References (5)

1. Y.-J. Jung et al., "A dual-loop delay-looked loop using multiple voltage-controlled delay line," IEEE J. Solid-State Circuits, vol. 36, pp. 784-791, May 2001.
2. T. H. Lee et al., "A 2.5V CMOS delay-looked loop for an 18 Mbit, 500 Megabyte/s DRAM," in IEEE J. Solid-State Circuits, vol 29, no. 12, pp. 1491-1496, Dec. 1994.
3. K.-H. Kim et al., "A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp. 212-213.
4. A. L. Coban, M. H. Koroglu, and K. A. Ahmed, "A 2.5-3.125Gb/s quad transceiver with second order analog DLL based CDRs," in Proc. IEEE Custom Integrated Circuits Conf., Oct. 2004, pp. 143-146.
5. B.-G. Kim and L-S. Kim, "A 250MHz - 2GHz wide range delay-locked loop," in Proc. IEEE Custom Integrated Circuits Conf., Oct. 2004, pp. 139-142.