An 8 Gb/s/pin 9.6 ns row-cycle 288 Mb deca-data rate SDRAM with an I/O error detection scheme

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 1, 2007, Pages 193-199

  Kim, Kyu Hyoun ^b   Chung, Hoe Ju ^c   Kim, Woo Seop ^a,c   Park, Moonsook ^c   Jang, Young Chan ^c   Kim, Jin Young ^c   Park, Hwan Wook ^c   Kang, Uksong ^a,c   Coteus, Paul W ^a,b   Choi, Joo Sun ^c   Kim, Changhyun ^a,c  

^a IEEE

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c SAMSUNG Electronics   (South Korea)

Author keywords

CRC; Deca data rate; Memory interface; Multi phase clock generation; Synchronous DRAM

Indexed keywords

DECA-DATA RATE; MEMORY INTERFACE; MULTIPHASE CLOCK GENERATION; SYNCHRONOUS DRAM;

BANDWIDTH; DATA STORAGE EQUIPMENT; ERROR ANALYSIS; INTERFACES (COMPUTER);

STATIC RANDOM ACCESS STORAGE;

EID: 33846198718     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.888297     Document Type: Article

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