A 512Mbit, 3.2Gbps/pin Packet-based DRAM with cost-efficient clock generation and distribution scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 36-37

  Sohn, Young Soo ^a   Choi, Jung Hwan ^a   Chung, In Young ^a   Chung, HoeJu ^a   Kim, Chan Kyoung ^a   Byun, Gyoung Su ^a   Kang, Dae Woon ^a   Park, Won Ki ^a   Park, In Soo ^a   Hwang, Hong Sun ^a   Kim, Chang Hyun ^a   Cho, Soo In ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COST EFFECTIVENESS; ELECTRIC CURRENT MEASUREMENT; ELECTRIC RESISTANCE; ENERGY UTILIZATION; OSCILLATIONS; PACKET NETWORKS; TRANSCEIVERS; VOLTAGE MEASUREMENT;

CURRENT MODE LOGIC (CML); ON-DIE TERMINATION (ODT); OSCILLATION FREQUENCIES; PROCESS-VOLTAGE-TEMPERATURE (PVT);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 4544345731     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. S.Sidiropoulos et al., "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffer," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2000, pp.124-127.
2. K.-Y.K.Chang et al., "A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2002, pp.88-91.