-
1
-
-
84934343547
-
Unlocking bandwidth for GPUs in CC-NUMA systems
-
presented at
-
N. Agarwal, D. Nellans, M. O'Connor, S. W. Keckler, and T. W. Wenisch, "Unlocking bandwidth for GPUs in CC-NUMA systems," presented at the International Symposium on High Performance Computer Architecture (HPCA), 2015.
-
(2015)
The International Symposium on High Performance Computer Architecture (HPCA)
-
-
Agarwal, N.1
Nellans, D.2
O'Connor, M.3
Keckler, S.W.4
Wenisch, T.W.5
-
2
-
-
84884899661
-
Hardware-accelerated regular expression matching with overlap handling on IBM poweren processor
-
K. Atasu, F. Doerfler, J. van Lunteren, and C. Hagleitner, "Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN Processor," in 2013 IEEE 27th International Symposium on Parallel Distributed Processing (IPDPS), 2013, pp. 1254-1265.
-
(2013)
2013 IEEE 27th International Symposium on Parallel Distributed Processing (IPDPS)
, pp. 1254-1265
-
-
Atasu, K.1
Doerfler, F.2
Van Lunteren, J.3
Hagleitner, C.4
-
3
-
-
80052550145
-
SpecTLB: A mechanism for speculative address translation
-
New York, NY, USA
-
T. W. Barr, A. L. Cox, and S. Rixner, "SpecTLB: A Mechanism for Speculative Address Translation," in Proceedings of the 38th Annual International Symposium on Computer Architecture, New York, NY, USA, 2011, pp. 307-318. Available: http://doi.acm.org/10.1145/2000064.2000101
-
(2011)
Proceedings of the 38th Annual International Symposium on Computer Architecture
, pp. 307-318
-
-
Barr, T.W.1
Cox, A.L.2
Rixner, S.3
-
4
-
-
77955012281
-
Translation caching: Skip, don't walk (the page table)
-
New York, NY, USA
-
T. W. Barr, A. L. Cox, and S. Rixner, "Translation Caching: Skip, Don'T Walk (the Page Table)," in Proceedings of the 37th Annual International Symposium on Computer Architecture, New York, NY, USA, 2010, pp. 48-59. Available: http://doi.acm.org/10.1145/1815961.1815970
-
(2010)
Proceedings of the 37th Annual International Symposium on Computer Architecture
, pp. 48-59
-
-
Barr, T.W.1
Cox, A.L.2
Rixner, S.3
-
5
-
-
84881179047
-
Efficient virtual memory for big memory servers
-
New York, NY, USA
-
A. Basu, J. Gandhi, J. Chang, M. D. Hill, and M. M. Swift, "Efficient Virtual Memory for Big Memory Servers," in Proceedings of the 40th Annual International Symposium on Computer Architecture, New York, NY, USA, 2013, pp. 237-248. Available: http://doi.acm.org/10.1145/2485922.2485943
-
(2013)
Proceedings of the 40th Annual International Symposium on Computer Architecture
, pp. 237-248
-
-
Basu, A.1
Gandhi, J.2
Chang, J.3
Hill, M.D.4
Swift, M.M.5
-
6
-
-
77957766305
-
Accelerating two-dimensional page walks for virtualized systems
-
New York, NY, USA
-
R. Bhargava, B. Serebrin, F. Spadini, and S. Manne, "Accelerating Two-dimensional Page Walks for Virtualized Systems," in Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, New York, NY, USA, 2008, pp. 26-35. Available: http://doi.acm.org/10.1145/1346281.1346286
-
(2008)
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 26-35
-
-
Bhargava, R.1
Serebrin, B.2
Spadini, F.3
Manne, S.4
-
7
-
-
84892513543
-
Large-reach memory management unit caches
-
New York, NY, USA
-
A. Bhattacharjee, "Large-reach Memory Management Unit Caches," in Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, New York, NY, USA, 2013, pp. 383-394. Available: http://doi.acm.org/10.1145/2540708.2540741
-
(2013)
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 383-394
-
-
Bhattacharjee, A.1
-
8
-
-
79955889568
-
Shared last-level tlbs for chip multiprocessors
-
Washington, DC, USA
-
A. Bhattacharjee, D. Lustig, and M. Martonosi, "Shared Last-level TLBs for Chip Multiprocessors," in Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture, Washington, DC, USA, 2011, pp. 62-63. Available: http://dl.acm.org/citation.cfm?id=2014698.2014896
-
(2011)
Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
, pp. 62-63
-
-
Bhattacharjee, A.1
Lustig, D.2
Martonosi, M.3
-
9
-
-
84934291132
-
Supporting superpages in non-contiguous physical memory
-
Y. Du, M. Zhou, B. R. Childers, D. Mosse, and R. Melhem, "Supporting superpages in non-contiguous physical memory," in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, pp. 223-234.
-
(2015)
2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)
, pp. 223-234
-
-
Du, Y.1
Zhou, M.2
Childers, B.R.3
Mosse, D.4
Melhem, R.5
-
10
-
-
84937691489
-
Efficient memory virtualization: Reducing dimensionality of nested page walks
-
Washington, DC, USA
-
J. Gandhi, A. Basu, M. D. Hill, and M. M. Swift, "Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks," in Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, 2014, pp. 178-189. Available: http://dx.doi.org/10.1109/MICRO.2014.37
-
(2014)
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 178-189
-
-
Gandhi, J.1
Basu, A.2
Hill, M.D.3
Swift, M.M.4
-
11
-
-
84893305304
-
The evolution of the arm architecture towards big data and the data-centre (abstract only)
-
New York, NY, USA
-
J. Goodacre, "The Evolution of the ARM Architecture Towards Big Data and the Data-centre (Abstract Only)," in Proceedings of the 8th Workshop on Virtualization in High-Performance Cloud Computing, New York, NY, USA, 2013, pp. 4:1-4:1. Available: http://doi.acm.org/10.1145/2535800.2535921
-
(2013)
Proceedings of the 8th Workshop on Virtualization in High-Performance Cloud Computing
, pp. 41
-
-
Goodacre, J.1
-
13
-
-
84960085139
-
Redundant memory mappings for fast access to large memories
-
New York, NY, USA
-
V. Karakostas, J. Gandhi, F. Ayar, A. Cristal, M. D. Hill, K. S. McKinley, M. Nemirovsky, M. M. Swift, and O. Ünsal, "Redundant Memory Mappings for Fast Access to Large Memories," in Proceedings of the 42Nd Annual International Symposium on Computer Architecture, New York, NY, USA, 2015, pp. 66-78. Available: http://doi.acm.org/10.1145/2749469.2749471
-
(2015)
Proceedings of the 42Nd Annual International Symposium on Computer Architecture
, pp. 66-78
-
-
Karakostas, V.1
Gandhi, J.2
Ayar, F.3
Cristal, A.4
Hill, M.D.5
McKinley, K.S.6
Nemirovsky, M.7
Swift, M.M.8
Ünsal, O.9
-
14
-
-
84892531872
-
Meet the walkers: Accelerating index traversals for in-memory databases
-
New York, NY, USA
-
O. Kocberber, B. Grot, J. Picorel, B. Falsafi, K. Lim, and P. Ranganathan, "Meet the Walkers: Accelerating Index Traversals for In-memory Databases," in Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, New York, NY, USA, 2013, pp. 468-479. Available: http://doi.acm.org/10.1145/2540708.2540748
-
(2013)
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 468-479
-
-
Kocberber, O.1
Grot, B.2
Picorel, J.3
Falsafi, B.4
Lim, K.5
Ranganathan, P.6
-
15
-
-
84934289942
-
Prediction-based superpage-friendly tlb designs
-
M.-M. Papadopoulou, X. Tong, A. Seznec, and A. Moshovos, "Prediction-based superpage-friendly TLB designs," in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, pp. 210-222.
-
(2015)
2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)
, pp. 210-222
-
-
Papadopoulou, M.-M.1
Tong, X.2
Seznec, A.3
Moshovos, A.4
-
18
-
-
84903973894
-
Increasing tlb reach by exploiting clustering in page translations
-
B. Pham, A. Bhattacharjee, Y. Eckert, and G. H. Loh, "Increasing TLB reach by exploiting clustering in page translations," in 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014, pp. 558-567.
-
(2014)
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
, pp. 558-567
-
-
Pham, B.1
Bhattacharjee, A.2
Eckert, Y.3
Loh, G.H.4
-
19
-
-
84876544775
-
Colt: Coalesced large-reach tlbs
-
Washington, DC, USA
-
B. Pham, V. Vaidyanathan, A. Jaleel, and A. Bhattacharjee, "CoLT: Coalesced Large-Reach TLBs," in Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, 2012, pp. 258-269. Available: http://dx.doi.org/10.1109/MICRO.2012.32
-
(2012)
Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 258-269
-
-
Pham, B.1
Vaidyanathan, V.2
Jaleel, A.3
Bhattacharjee, A.4
-
20
-
-
84959876132
-
Large pages and lightweight memory management in virtualized environments: Can you have it both ways
-
presented at
-
B. Pham, J. vesely, G. Loh, and A. Bhattacharjee, "Large Pages and Lightweight Memory Management in Virtualized Environments: Can You Have it Both Ways," presented at the IEEE/ACM International Symposium on Microarchitecture (MICRO), 2015.
-
(2015)
The IEEE/ACM International Symposium on Microarchitecture (MICRO)
-
-
Pham, B.1
Vesely, J.2
Loh, G.3
Bhattacharjee, A.4
-
21
-
-
84897759661
-
Architectural support for address translation on GPUs: Designing memory management units for cpu/GPUs with unified address spaces
-
New York, NY, USA
-
B. Pichai, L. Hsu, and A. Bhattacharjee, "Architectural Support for Address Translation on GPUs: Designing Memory Management Units for CPU/GPUs with Unified Address Spaces," in Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems, New York, NY, USA, 2014, pp. 743-758. Available: http://doi.acm.org/10.1145/2541940.2541942
-
(2014)
Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 743-758
-
-
Pichai, B.1
Hsu, L.2
Bhattacharjee, A.3
-
22
-
-
84903978286
-
Supporting x86-64 address translation for 100s of GPU lanes
-
J. Power, M. D. Hill, and D. A. Wood, "Supporting x86-64 address translation for 100s of GPU lanes," in 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014, pp. 568-578.
-
(2014)
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
, pp. 568-578
-
-
Power, J.1
Hill, M.D.2
Wood, D.A.3
-
23
-
-
84995591094
-
Towards cache-friendly hardware accelerators
-
Y. Sophia Shao, S. Xi, V. Srinivasan, G.-Y. Wei, and D. Brooks, "Towards Cache-Friendly Hardware Accelerators," in HPCA Sensors and Cloud Architectures Workshop (SCAW), 2015. Available: http://www.eecs.harvard.edu/~shao/papers/shao2015-scaw.pdf
-
(2015)
HPCA Sensors and Cloud Architectures Workshop (SCAW)
-
-
Sophia Shao, Y.1
Xi, S.2
Srinivasan, V.3
Wei, G.-Y.4
Brooks, D.5
-
24
-
-
84922876530
-
Capi: A coherent accelerator processor interface
-
Jan.
-
J. Stuecheli, B. Blaner, C. R. Johns, and M. S. Siegel, "CAPI: A Coherent Accelerator Processor Interface," IBM J. Res. Dev., vol. 59, no. 1, pp. 7:1-7:7, Jan. 2015.
-
(2015)
IBM J. Res. Dev.
, vol.59
, Issue.1
, pp. 71-77
-
-
Stuecheli, J.1
Blaner, B.2
Johns, C.R.3
Siegel, M.S.4
-
25
-
-
84856515634
-
Didi: Mitigating the performance impact of tlb shootdowns using a shared tlb directory
-
C. Villavieja, V. Karakostas, L. Vilanova, Y. Etsion, A. Ramirez, A. Mendelson, N. Navarro, A. Cristal, and O. S. Unsal, "DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory," in 2011 International Conference on Parallel Architectures and Compilation Techniques (PACT), 2011, pp. 340-349.
-
(2011)
2011 International Conference on Parallel Architectures and Compilation Techniques (PACT)
, pp. 340-349
-
-
Villavieja, C.1
Karakostas, V.2
Vilanova, L.3
Etsion, Y.4
Ramirez, A.5
Mendelson, A.6
Navarro, N.7
Cristal, A.8
Unsal, O.S.9
-
26
-
-
84888413773
-
-
"HSA Foundation.". Available: http://www.hsafoundation. com/
-
HSA Foundation
-
-
-
27
-
-
84870669626
-
-
"PCI Express.". Available: https://en.wikipedia. org/wiki/PCI-Express
-
PCI Express
-
-
|