-
1
-
-
0027561268
-
Processor Reconfiguration Through Instruction-Set Metamorphosis
-
March
-
Athanas, P., and H. Silverman. Processor Reconfiguration Through Instruction-Set Metamorphosis. Computer, vol. 26 no. 3, March 1993 pp. 11-18.
-
(1993)
Computer
, vol.26
, Issue.3
, pp. 11-18
-
-
Athanas, P.1
Silverman, H.2
-
2
-
-
0036469457
-
Mapping a Single Assignment Programming Language to Reconfigurable Systems
-
Bohm, W., J. Hammes, B. Draper, M. Chawathe, C. Ross, R. Rinker, and W. Najjar. Mapping a Single Assignment Programming Language to Reconfigurable Systems. Supercomputing, vol. 21, pp. 117-130, 2002.
-
(2002)
Supercomputing
, vol.21
, pp. 117-130
-
-
Bohm, W.1
Hammes, J.2
Draper, B.3
Chawathe, M.4
Ross, C.5
Rinker, R.6
Najjar, W.7
-
3
-
-
84963944073
-
One-Step Compilation of Image Processing Applications to FPGAs
-
Rohnert Park, CA, April 30-May 2
-
Bohm, W., B. Draper, W Najjar, J. Hammes, R. Rinker, M. Chawathe, and C. Ross. One-Step Compilation of Image Processing Applications to FPGAs. In IEEE Symposium on Field-Programmable Custom Computing Machines, Rohnert Park, CA, April 30-May 2, 2001.
-
(2001)
IEEE Symposium on Field-Programmable Custom Computing Machines
-
-
Bohm, W.1
Draper, B.2
Najjar, W.3
Hammes, J.4
Rinker, R.5
Chawathe, M.6
Ross, C.7
-
4
-
-
0003510233
-
-
University of Wisconsin-Madison, Computer Science Department, Technical Report CS-TR-1308, July
-
Burger, D.,T. Austin and S. Bennett. Evaluating Future Microprocessors: The SimpleScalarToolSet. University of Wisconsin-Madison, Computer Science Department, Technical Report CS-TR-1308, July 1996.
-
(1996)
Evaluating Future Microprocessors: The SimpleScalarToolSet
-
-
Burger, D.1
Austin, T.2
Bennett, S.3
-
5
-
-
0030784055
-
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search
-
Jan.
-
Eles, P., Z. Peng, K. Kuchchinski, and A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Kluwer's Design Automation for EmbeddedSystems, vol. 2, no. 1, pp. 5-32, Jan. 1997.
-
(1997)
Kluwer's Design Automation for EmbeddedSystems
, vol.2
, Issue.1
, pp. 5-32
-
-
Eles, P.1
Peng, Z.2
Kuchchinski, K.3
Doboli, A.4
-
8
-
-
0033884908
-
A Configurable and Extensible Processor
-
Gonzalez, R. and R E. Xtensa. A Configurable and Extensible Processor. IEEE Micro, pp. 60-70, 2000.
-
(2000)
IEEE Micro
, pp. 60-70
-
-
Gonzalez, R.1
Xtensa, R.E.2
-
10
-
-
84981187146
-
Loop Fusion and Temporal Common Subexpression Elimination in Window-Based Loops
-
San Francisco, CA, April 27
-
Hammes, J., W. Bohm, C. Ross, M. Chawathe, B. Draper, R. Rinker, and W. Najjar. Loop Fusion and Temporal Common Subexpression Elimination in Window-Based Loops. In IPDPS 8th Reconfigurable Architectures Workshop, San Francisco, CA, April 27, 2001.
-
(2001)
IPDPS 8th Reconfigurable Architectures Workshop
-
-
Hammes, J.1
Bohm, W.2
Ross, C.3
Chawathe, M.4
Draper, B.5
Rinker, R.6
Najjar, W.7
-
11
-
-
52549091144
-
A High-Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems
-
The 2nd International Workshop on the Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), LasVegas, NV, June 26-29
-
Hammes, J., R Rinker, W Najjar, and B. Draper. A High-Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems. In The 2nd International Workshop on the Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), part of the 2000 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), LasVegas, NV, June 26-29,2000.
-
(2000)
2000 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA)
-
-
Hammes, J.1
Rinker, R.2
Najjar, W.3
Draper, B.4
-
12
-
-
0031360911
-
Garp: A MIPS Processor with a Reconfigurable Coprocessor
-
Napa Valley, CA, April
-
Hauser, J. and J. Wawrzynek. Garp: A MIPS Processor With a Reconfigurable Coprocessor. In IEEE Symposium on FPGAsfor Custom Computing Machines, pages 12-21, Napa Valley, CA, April 1997.
-
(1997)
IEEE Symposium on FPGAsfor Custom Computing Machines
, pp. 12-21
-
-
Hauser, J.1
Wawrzynek, J.2
-
15
-
-
0031101366
-
The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling and Implementation-Bin Selection
-
Mar.
-
Kalavade, A. and E. A. Lee. The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling and Implementation-Bin Selection. Kluwer Design Automation for Embedded Systems, vol. 2, no. 2, pp. 125-163, Mar. 1997.
-
(1997)
Kluwer Design Automation for Embedded Systems
, vol.2
, Issue.2
, pp. 125-163
-
-
Kalavade, A.1
Lee, E.A.2
-
17
-
-
0031339427
-
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems
-
Dec.
-
Lee, C., M. Potkonjak, and W H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, Proc. 30th Annual International Symposium on Microarchitecture, Dec. 1997, pp. 330-335.
-
(1997)
Proc. 30th Annual International Symposium on Microarchitecture
, pp. 330-335
-
-
Lee, C.1
Potkonjak, M.2
Mangione-Smith, W.H.3
-
18
-
-
0011291883
-
-
MIPS Technologies, Inc.
-
MIPS Technologies, Inc. http: //www.mips.com.
-
-
-
-
20
-
-
0011362896
-
-
Synplicity
-
Synplicity, www.synplicity.com/products/synplifypro.html.
-
-
-
-
21
-
-
0011376501
-
-
Triscend Corporation
-
Triscend Corporation, http: //www.triscend.com.
-
-
-
-
22
-
-
52549131117
-
-
UCRDalton Project
-
UCRDalton Project, http://www.cs.ucr.edu/~dalton/.
-
-
-
-
24
-
-
0011328042
-
-
Virtex Power Estimator
-
Virtex Power Estimator, http://support.xilinx.com/cgi-bin/powerweb.pl.
-
-
-
|