-
2
-
-
0027834702
-
A BIST Scheme for a SNR Test of a Sigma-Delta ADC
-
M. F. Toner and G. W. Roberts: "A BIST Scheme for a SNR Test of a Sigma-Delta ADC". Proc. IEEE Int. Test Conf., pp.805-814, 1993.
-
(1993)
Proc. IEEE Int. Test Conf.
, pp. 805-814
-
-
Toner, M.F.1
Roberts, G.W.2
-
6
-
-
0033743777
-
Hardware Minimization for an Histogram-based ADC BIST
-
M. Renovell et al.: "Hardware Minimization for an Histogram-based ADC BIST". Proc. 18th IEEE VLSI Test Symposium, pp.247-252, 2000.
-
(2000)
Proc. 18th IEEE VLSI Test Symposium
, pp. 247-252
-
-
Renovell, M.1
-
7
-
-
0033309978
-
Testing High Speed High Accuracy Analog to Digital Converters Embedded in System on Chip
-
S. Max: "Testing High Speed High Accuracy Analog to Digital Converters Embedded in System on Chip". Proc. Int. Test Conf., pp.763-771, 1999.
-
(1999)
Proc. Int. Test Conf.
, pp. 763-771
-
-
Max, S.1
-
8
-
-
0031357811
-
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
-
S. K. Sunter and N. Nagi: "A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST". Proc. Int. Test Conf., pp.389-395, 1997.
-
(1997)
Proc. Int. Test Conf.
, pp. 389-395
-
-
Sunter, S.K.1
Nagi, N.2
-
9
-
-
0021586344
-
Full-Speed Testing of A/d Converters
-
J. Doernberg: "Full-Speed Testing of A/d Converters". IEEE Journal of Solid-State Circuits, pp.820-7, vol sc-19, no 6, 1984.
-
(1984)
IEEE Journal of Solid-State Circuits
, vol.SC-19
, Issue.6
, pp. 820-827
-
-
Doernberg, J.1
-
10
-
-
84965154339
-
An Embedded Servo loop for Testing ADC Linearity
-
Z. Zhao and A. Ivanoz: "An Embedded Servo loop for Testing ADC Linearity". Proc. Int. Test Conf., pp.24-34, 2001.
-
(2001)
Proc. Int. Test Conf.
, pp. 24-34
-
-
Zhao, Z.1
Ivanoz, A.2
-
11
-
-
0037859112
-
Implementation of a Linear Histogram BIST for ADC
-
F. Azaïs et al.: "Implementation of a Linear Histogram BIST for ADC". Proc. Int. Test Conf., pp.590-595, 2000.
-
(2000)
Proc. Int. Test Conf.
, pp. 590-595
-
-
Azaïs, F.1
-
12
-
-
0034476235
-
Optimal INL/DNL Testing of A/D Converters Using Linear Model
-
S. Cherubal and A. Chatterjee: "Optimal INL/DNL Testing of A/D Converters Using Linear Model". Proc. Int. Test Conf., pp.358-366, 2000.
-
(2000)
Proc. Int. Test Conf.
, pp. 358-366
-
-
Cherubal, S.1
Chatterjee, A.2
-
13
-
-
0034479554
-
Mearuring Code Edges of ADCs Using Interpolation and Its Application to Offset and Gain Error Testing
-
P. N. Variyam and V. Agrawal: "Mearuring Code Edges of ADCs Using Interpolation and Its Application to Offset and Gain Error Testing". Proc. Int. Test Conf., pp.349-357, 2000.
-
(2000)
Proc. Int. Test Conf.
, pp. 349-357
-
-
Variyam, P.N.1
Agrawal, V.2
-
14
-
-
0033353554
-
Estimating the Integral Non-Linearity of AD-Converters via Frequency Domain
-
N. Csizmadia and A. J. E. M. Janssen: "Estimating the Integral Non-Linearity of AD-Converters via Frequency Domain." Proc. Int. Test Conf., pp.757-761, 1999.
-
(1999)
Proc. Int. Test Conf.
, pp. 757-761
-
-
Csizmadia, N.1
Janssen, A.J.E.M.2
-
20
-
-
0013277082
-
Efficient on-chip generator for linear histogram BIST of ADCs
-
S. Bernard et al.: "Efficient on-chip generator for linear histogram BIST of ADCs". Proc. IEEE Int. Mixed-Signal Testing Workshop, pp. 86-96, 2001.
-
(2001)
Proc. IEEE Int. Mixed-Signal Testing Workshop
, pp. 86-96
-
-
Bernard, S.1
-
21
-
-
0038535605
-
Estimating Static Parameters of A-to-D Converters from Spectral Analysis
-
F. Azaïs et al.: "Estimating Static Parameters of A-to-D Converters from Spectral Analysis". Proc. 3rd IEEE Latin-American Test Workshop, pp174-179, 2002.
-
(2002)
Proc. 3rd IEEE Latin-American Test Workshop
, pp. 174-179
-
-
Azaïs, F.1
|