BIST for D/A and A/D converters

IEEE Design and Test of Computers

Volumn 13, Issue 4, 1996, Pages 40-49

  Arabi, Karim ^a,c   Kaminska, Bozena ^a,b,d   Rzeszut, Janusz ^b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^c AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

^d IEEE

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; AUTOMATIC TESTING; BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

BUILT IN SELF TEST (BIST); DIFFERENTIAL NONLINEARITY; GAIN ERROR; INTEGRAL NONLINEARITY; OFFSET VOLTAGE;

INTEGRATED CIRCUIT TESTING;

EID: 0030402730     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.544535     Document Type: Review

References (12)

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2. M.F. Toner and G.W. Roberts, "A BIST Scheme for an SNR Test of a Sigma-Delta ADC," Proc. Int'l Test Conf., IEEE CS Press, 1993, pp. 805-814.
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11. C. Browing, "Testing A/D Converters on Microprocessors," Proc. Int'l Test Conf., IEEE CS Press, 1985, pp. 818-824.
12. M. Song, Y. Lee, and W. Kim, "A Clock Feedthrough Reduction Circuit for Switched-Current Systems," IEEE J. of Solid-State Circuits, Vol. 28, No. 2, Feb. 1993, pp. 133-137.