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A 45 nm logic technology with high k + metal gate transistors strained silicon 9 Cu interconnect layers 193nm dry patterning and 100% Pb-free packaging
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K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki A 45 nm logic technology with high k + metal gate transistors strained silicon 9 Cu interconnect layers 193nm dry patterning and 100% Pb-free packaging IEDM Tech. Dig. 2007 247
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High-performance and low-power CMOS device technologies featuring metal/high-k gate stacks with uniaxial strained silicon channels on (1 0 0) and (1 1 0) substrates
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Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kitamura, T. Ochiai, Y. Yamamoto, Y. Nagahama, Y. Hagimito, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, and N. Nagashima High-performance and low-power CMOS device technologies featuring metal/high-k gate stacks with uniaxial strained silicon channels on (1 0 0) and (1 1 0) substrates IEDM Tech. Dig. 2006 63
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45 nm high-k + metal gate strain-enhanced transistors
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High-k/metal gate stacks in gate first and replacement gate schemes
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S. Kesapragada, R. Wang, D. Liu, G. Liu, Z. Xie, Z. Ge, H. Yang, Y. Lei, X. Lu, X. Tang, J. Lei, M. Allen, S. Gandikota, K. Moraes, S. Hung, N. Yoshida, and C.P. Chang High-k/metal gate stacks in gate first and replacement gate schemes Proc. ASMC 2010 256
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Chemical mechanical planarization: Slurry chemistry materials and mechanisms
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Extreme high-performance n- and p-MOSFETs boosted by dual-metal/high-k gate damascene process using top-cut dual stress liners on (1 0 0) substrates
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S. Mayuzumi, J. Wang, S. Yamakawa, Y. Tateshita, T. Hirano, M. Nakata, S. Yamaguchi, Y. Yamamoto, Y. Miyanami, I. Oshiyama, K. Tanaka, K. Tai, K. Ogawa, K. Kugimiya, Y. Nagahama, Y. Hagimoto, R. Yamamoto, S. Kanda, K. Nagano, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, and N. Nagashima Extreme high-performance n- and p-MOSFETs boosted by dual-metal/high-k gate damascene process using top-cut dual stress liners on (1 0 0) substrates IEDM Tech. Dig. 2007 293
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S. Mayuzumi, S. Yamakawa, Y. Tateshita, T. Hirano, M. Nakata, S. Yamaguchi, K. Tai, H. Wakabayashi, M. Tsukamoto, and N. Nagashima High-performance metal/high-k n- and p-MOSFETs with top-cut dual stress liners using gate-last damascene process on (1 0 0) substrates IEEE Trans. Electron Dev. 56 2009 620
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High performance 32 nm logic technology featuring 2nd generation high k + metal gate transistors
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Study of wetting properties of Ti/TiN liners deposited by ion metal plasma PVD for low-temperature sub-0.25-um Al fill technology
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Simon Hui, Ken Ngan, Murali K. Narasimhan, Barry Hogan, Gongda Yao, and Sesh Ramaswami Study of wetting properties of Ti/TiN liners deposited by ion metal plasma PVD for low-temperature sub-0.25-um Al fill technology Proc. SPIE 3214 1997 79
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