Impact of CMOS device scaling in ASICs on radiation immunity

1st Egyptian Workshop on Advancements of Electronic Devices, EWAED 2002

Volumn , Issue , 2002, Pages 18-27

  Ragaie, H ^a   Kayed, S ^b  

^a Ain Shams University   (Egypt)

^b NUCLEAR MATERIALS AUTHORITY   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON DEVICES; ELECTRONIC EQUIPMENT; FLASH MEMORY; HEAVY IONS; RADIATION HARDENING; THERMOELECTRIC EQUIPMENT;

CMOS DEVICE SCALING; DEEP SUBMICRON CMOS; DEVICE-SCALING; FEATURE SIZES; RADIATION IMMUNITY; SINGLE EVENT UPSETS; SPACE ENVIRONMENT; TOTAL IONIZATION DOSE EFFECTS;

RADIATION EFFECTS;

EID: 84962173550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EWAED.2002.1177875     Document Type: Conference Paper

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