RC power bus maximum voltage drop in digital VLSI circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 205-210

  Bai, G ^a   Bobba, S ^a   Hajj, I N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SENSITIVITY ANALYSIS; SPICE; TIMING CIRCUITS;

CIRCUIT TIMING; CLOCK CYCLES; GATE CURRENT; HSPICE SIMULATIONS; OPTIMIZATION PROCEDURES; STATISTICAL VARIATIONS; SUB-INTERVAL; VOLTAGE DROP;

VLSI CIRCUITS;

EID: 84949936414     PISSN: 19483287     EISSN: 19483295     Source Type: Journal    
DOI: 10.1109/ISQED.2001.915228     Document Type: Article

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